FOR AUTOMOTIVE 105

°C OPERATION 2-WIRE SERIAL E

S-24CS01A/02A/04A H Series

12

6. Write

6. 1 Byte write

When the master sends a 7-bit device address and a 1-bit read / write instruction code set to "0", following a start

condition, the S-24CS01A/02A/04A acknowledges it. The S-24CS01A/02A/04A then receives an 8-bit word address

and responds with an acknowledge. After the S-24CS01A/02A/04A receives 8-bit write data and responds with an

acknowledge, it receives a stop condition and that initiates the write cycle at the addressed memory.

During the write cycle all operations are forbidden and no acknowledge is generated.

A2 A1 A0

S

T

A

R

T

1

0 1

0

W

R

I

T

E

DEVICE

ADDRESS

R

/

W

M

S

B

SDA LINE

ADR INC

(ADDRESS INCREMENT)

A

C

K

L

S

B

0

WORD ADDRESS

S

T

O

P

DATA

W7 W6 W5 W4 W3 W2 W1 W0

D7 D6 D5 D4 D3 D2 D1 D0

A

C

K

A

C

K

Remark 1.

A0 is P0 in the S-24CS04A.

2.

W7 is optional in the S-24CS01A.

Figure 12 Byte Write