VSP2264 datasheet(13/63 Pages) TI

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Theory of Operation

SLES059—March 2003

VSP2264

Theory of Operation

2.1

Introduction

The VSP2264 is a high-resolution mixed-signal IC that contains key features associated with the processing

of the CCD signal in a digital still camera (DSC). The VSP2264 integrates the analog front end (AFE) and CCD

timing generator (TG) with the H and R drivers.

The AFE block includes a correlated double sampler (CDS), 14-bit analog-to-digital converter (ADC), digital

gain amplifier, black-level clamp loop, input clamp, CDS timing generator, and voltage reference. The built-in

TG generates not only horizontal (H-rate) timing, but also vertical (V-rate) timing for the specified CCD model.

Optimized timing is generated by selecting the CCD model and operating mode through the serial interface.

2.2

Timing Generator (TG)

The TG generates both H-rate timing and V-rate timing.

Figure 2–1 shows a high-speed timing block of the TG. This part generates six high-speed pulses for H-rate

timing such as R, H1 and HL/H2, SHP/SHD, and ADCCK. These high-speed pulses are generated from the

master clock, which has a speed of twice the pixel rate. The serial interface sets the amount of phase

adjustment for these high-speed pulses in 16 steps (8 steps for R) with a minimum 0.6-ns pitch (four steps

of 0.6 ns and four steps of 1.2 ns for R). The power mode controls the output driver enable/disable. An on-chip

decoder calculates H clear according to the CCD model and operating mode. H1, HL, H2, and R can drive

the CCD directly. The ADCCK, SHP, and SHD, signals support both the internal generation mode and the

external supply mode.

VSP2264 Datasheet(PDF) 13 Page - Texas Instruments