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SAM2653

11- RECOMMENDED BOARD LAYOUT

Like all HCMOS high integration ICs, following simple rules of board layout is mandatory

for reliable operations:

 GND, VD33 distribution, decoupling

All GND, AGND, VD33, VA33 pins should be connected. A GND plane is strongly

recommended below the SAM2653. The board GND + VD33 planes could be in grid

form to minimize EMI.

Recommended decoupling is 4.7 or 10µF close to OUTVC12 pin. VD33 requires 0.1uF

at each corner of the IC with an additional 10µFT capacitor should be placed close to

the crystal.

 Crystal

The paths between the crystal, the crystal compensation capacitors and the SAM2653

should be short and shielded. The ground return from the compensation capacitors

should be the GND plane from SAM2653.

 Busses

Parallel layout from DB0-DB7 and WA0-WA24/WD0-WD15 should be avoided. The

DB0-DB7 bus is an asynchronous type bus. Even on short distances, it can induce

pulses on WA0-WA24/WD0-WD15 which can corrupt address and/or data on these

busses.

A ground plane should be implemented below the DB0-DB7 bus.

A ground plane should be implemented below the WA0-WA24/WD0-WD15 bus, which

connects both to the ROM/Flash grounds and to the SAM2653.

 Analog section

A specific AGND ground plane should be provided, which connects by a single trace to

the GND ground. No digital signals should cross the AGND plane. Refer to the Codec

vendor recommended layout for correct implementation of the analog section.