AV-51001 datasheet(13/40 Pages) ALTERA

13 / 40 page

Resource

Member Code

FPGA GPIO(8)

540

HPS I/O

208

LVDS

Transmitter

120

Receiver

136

PCIe Hard IP Block

FPGA Hard Memory Controller

HPS Hard Memory Controller

ARM Cortex-A9 MPCore Processor

Dual-core

Related Information

High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device

Handbook

Provides the number of LVDS channels in each device package.

Package Plan

Table 11: Package Plan for Arria V SX Devices

The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific

I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

Member

Code

F896

(31 mm)

F1152

(35 mm)

F1517

(40 mm)

FPGA

GPIO

HPS I/O

XCVR

FPGA

GPIO

HPS I/O

XCVR

FPGA

GPIO

HPS I/O

XCVR

250

208

385

208

540

208

250

208

385

208

540

208

Arria V ST

This section provides the available options, maximum resource counts, and package plan for the

Arria V ST devices.

The information in this section is correct at the time of publication. For the latest information and to get

more details, refer to the Altera Product Selector.

Related Information

Altera Product Selector

Provides the latest information about Altera products.

(8)

The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user

I/Os includes transceiver I/Os.

AV-51001

2015.01.23

Package Plan

Arria V Device Overview

Altera Corporation

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