4
CS3810 32 QAM Demodulator
CLL SETTINGS
INIPCLL
Input
1
CLL initial period selection, in terms of 32-QAM symbols, static program-
ming signal,
0: 16384
1: 32768
When the BLL lock is declared, the CLL switches from idle state to initial
state in which the equalizer is put into CMA mode. The CLL acquisition
starts after the initial period.
AFCCLL
Input
1
Use or not use AFC for frequency offset estimate, static programming
signal
0: do not use AFC
1: use AFC
When AFC is not in use, the CLL uses a scan counter mechanism to
estimate the frequency offset. Every time when the pull-in fails the
counter is increased by one to give a new frequency offset value until the
lock is achieved.
NAFCCLL
Input
1
Number of AFC computations for averaging in AFC period
0: 16
1: 64
Simulation shows that in noisy conditions selection of 64 gives more reli-
able frequency offset estimate
PILBWCLL
Input
1
CLL pull-in (acquisition) mode bandwidth select
0: 0.0015(55KHz)
1: 0.003(110KHz)
The bandwidth is approximated based on the assumption of damping
factor of 0.71
DDLBWCLL
Input
1
CLL decision-direct (tracking) mode bandwidth select
0: 0.01(370KHz)
1: 0.02(740KHz)
The bandwidth is approximated based on the assumption of damping
factor of 0.71
MUCMAEQ
Input
2
Equalizer m select for CMA mode
00: 1/1024
01: 1/512
10: 1/256
11: 1/128
MUDDEQ
Input
2
Equalizer m select for DD LMS mode
00: 1/8192
01: 1/4096
10: 1/2048
11: 1/1024
OUTPUT DATA
RXSYNC
Output
1
Output ready flag. Signals that valid output data is present at the
RXDATA port
RXDATA
Output
8
Received output data port
Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions
Name
I/O
Width
Description
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