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CS3810 32 QAM Demodulator
TIMING CHARACTERISTICS
The programming signals are assumed to be static, i.e., they
do not change during normal operation process. The
microprocessor interface signals have been described in the
previous section. The timing diagrams of the other signals are
provided below, with reference to the clock and output
sample strobe signals.
Figure 4: Input Data Timing
Figure 5: AGC Control Timing
Figure 6: Test Data Timing
CLK
ZA
ZB
CLK
AGCP
AGCOK
ZSTRB
512 cycles (256 symbols)
CLK
BLLIQ
BLLQI
BLLSTRB
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