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EPVP6300 Datasheet(PDF) 21 Page - ELAN Microelectronics Corp |
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EPVP6300 Datasheet(HTML) 21 Page - ELAN Microelectronics Corp |
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21 / 63 page ![]() ePVP6300 VFD Controller This specification is subject to change without further notice. 11/04 .2004 (V1.92)15 of 63 This is a CMOS multi-channel 10-bit successive approximation A/D converter. Features: 74.6kHz maximum conversion speed at 5V Adjusted full scale input External reference voltage input or internal (VDD) reference voltage 6 analog inputs multiplexed into one A/D converter Power down mode for power saving A/D conversion complete interrupt Interrupt register, A/D control and status register, and A/D data register Fig. 5 ADC Voltage Control Logic fadcon = fadc / 12 fpll Mx fs Nx = 1 Nx = 2 Nx = 4 Nx = 8 14.331MHz 16 895.658kHz 74.638kHz 37.391kHz 18.659khz 9.329kHz 10.747MHz 12 895.658kHz 74.638kHz 37.391kHz 18.659khz 9.329kHz 7.165MHz 8 895.658kHz 74.638kHz 37.391kHz 18.659khz 9.329kHz 3.582MHz 4 895.658kHz 74.638kHz 37.391kHz 18.659khz 9.329kHz 1.791MHz 2 895.658kHz 74.638kHz 37.391kHz 18.659khz 9.329kHz 895.658kHz 1 895.658kHz 74.638kHz 37.391kHz 18.659khz 9.329kHz 447.829kHz 1 447.829kHz 37.391kHz 18.659khz 9.329kHz 4.665kHz Bit 5 ~ Bit 7 (IN0 ~ IN2) : Input channel selection of AD converter These two bits can choose one of the three AD inputs. IN2 IN1 IN0 Input 0 0 0 AD1 0 0 1 AD2 0 1 0 AD3 0 1 1 AD4 1 0 0 AD5 1 0 1 AD6 Programmable divider 1/Mx Divider Nx 10-bit ADC ADCLK1~ADCLK0 fs ADC output PLL ENPLL CLK2 ~ CLK0 fpll fad c |
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