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DLPC900ZPC Datasheet(PDF) 35 Page - Texas Instruments |
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DLPC900ZPC Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 83 page ![]() tc tw(H) SSPx_CLK (ASIC output) 50% 20% 50% 50% tw(L) tt Valid SSPx_DO (ASIC output) tpd(max) tpd(min) Valid tsu Valid th Valid 50% Valid SSPx_CSZ SSPx_DI (ASIC input) 80% tc tw(H) SSPx_CLK (ASIC output) 50% 20% 50% 50% tw(L) tt Valid SSPx_DO (ASIC output) tpd(max) tpd(min) Valid tsu Valid SSPx_DI (ASIC input) th Valid 50% Valid SSPx_CSZ 80% CLK (CPOL = 0) (CPOL = 1) CSZ DI/DO (CPHA = 0) (CPHA = 1) MSB LSB MSB LSB 35 DLPC900 www.ti.com DLPS037D – OCTOBER 2014 – REVISED MARCH 2019 Product Folder Links: DLPC900 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Figure 9. SSP Clock Mode Timing Diagram Figure 10. Synchronous Serial Port Interface – Master (Modes 0/3) Figure 11. Synchronous Serial Port Interface – Slave (Modes 0/3) |
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