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HD49335F Datasheet(PDF) 10 Page - Renesas Technology Corp

Part # HD49335F
Description  CDS/PGA AND 10-bit A/D TG Converter
PDF  30 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD49335F Datasheet(HTML) 10 Page - Renesas Technology Corp

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HD49335F/HF
Rev.1.0, Feb.25.2004, page 10 of 29
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
012
9
10
11
N+1
N+2
N+9
N+10
N+11
N
CDS_in
SP1
SP2
ADCLK
D0 to D9
N+2
N+8
N+9
N+10
N+11
N
−8
N
−9N−1
ADC_in
ADCLK
D0 to D9
N
N+1
N
N+1
N
−9N−8N−1
N
N
−10
• When CDS_in input mode is used
• When ADC_in input mode is used
~
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
• The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.
• Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used.
• In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.



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