CS4364 datasheet(17/50 Pages) CIRRUS

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DS619A1

CS4364

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT

(Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF)

Notes:

18. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

19. Data must be held for sufficient time to bridge the transition time of CCLK.

20. For FSCK < 1 MHz.

Parameter

Symbol

Min

Max

Unit

CCLK Clock Frequency

fsclk

-6

MHz

RST Rising Edge to CS Falling

tsrs

500

CCLK Edge to CS Falling

(Note 18)

tspi

500

CS High Time Between Transmissions

tcsh

1.0

µs

CS Falling to CCLK Edge

tcss

CCLK Low Time

tscl

CCLK High Time

tsch

CDIN to CCLK Rising Setup Time

tdsu

CCLK Rising to DATA Hold Time

(Note 19)

tdh

Rise Time of CCLK and CDIN

(Note 20)

tr2

-100

Fall Time of CCLK and CDIN

(Note 20)

tf2

-100

t r2

t f2

t dsu t dh

t sch

t scl

CCLK

CDIN

t css

t csh

t spi

t srs

RST

Figure 6. Control Port Timing - SPI Format

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