CS5342

DS608PP2

11

* For a description of Speed Modes, please refer to Table 1 on page 15

Notes: 9. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48.

Parameter

Symbol

Min

Typ

Max

Unit

MCLK Specifications

MCLK Period

26

-

31

ns

52

-

1303

ns

MCLK Pulse Duty Cycle

40

-

60

%

Master Mode

SCLK falling to LRCK

-20

-

20

ns

SCLK falling to SDOUT valid

-

-

32

ns

SCLK Duty Cycle

Single-Speed

Double-Speed

Quad-Speed

-

-

-

50

50

33

-

-

-

%

%

%

Slave Mode

Single Speed*

LRCK Duty Cycle

40

-

60

%

SCLK Period

290

-

-

ns

SCLK Duty Cycle

45

-

55

%

SDOUT valid before SCLK rising

10

-

-

ns

SDOUT valid after SCLK rising

5-

-

ns

SCLK falling to LRCK edge

-20

-

20

ns

Double Speed*

LRCK Duty Cycle

40

-

60

%

SCLK Period (Note 9)

193

-

-

ns

SCLK Duty Cycle

45

-

55

%

SDOUT valid before SCLK rising

10

-

-

ns

SDOUT valid after SCLK rising

5-

-

ns

SCLK falling to LRCK edge

-20

-

20

ns

Quad Speed* (Note 2)

LRCK Duty Cycle

40

-

60

%

SCLK Period (Note 9)

104

-

-

ns

SCLK Duty Cycle

40

-

50

%

SDOUT valid before SCLK rising

10

-

-

ns

SDOUT valid after SCLK rising

5-

-

ns

SCLK falling to LRCK edge

-8

-

8

ns