CS5342

DS608PP2

3

LIST OF FIGURES

Figure 1. Single Speed Stopband Rejection .................................................................................. 8

Figure 2. Single Speed Stopband Rejection (detail) ...................................................................... 8

Figure 3. Single Speed Transition Band (detail) ............................................................................ 8

Figure 4. Single Speed Passband Ripple ...................................................................................... 8

Figure 5. Double Speed Stopband Rejection ................................................................................. 8

Figure 6. Double Speed Stopband Rejection (detail) ..................................................................... 8

Figure 7. Double Speed Transition Band (detail) ........................................................................... 9

Figure 8. Double Speed Passband Ripple ..................................................................................... 9

Figure 9. Quad Speed Stopband Rejection ................................................................................... 9

Figure 10. Quad Speed Stopband Rejection (detail) ..................................................................... 9

Figure 11. Quad Speed Transition Band (detail) ............................................................................ 9

Figure 12. Quad Speed Passband Ripple ...................................................................................... 9

Figure 13. Master Mode, Left Justified SAI .................................................................................. 12

Figure 14. Slave Mode, Left Justified SAI .................................................................................... 12

Figure 15. Master Mode, I2S SAI ................................................................................................. 12

Figure 17. Typical Connection Diagram ....................................................................................... 14

Figure 18. CS5342 Master Mode Clocking .................................................................................. 16

Figure 19. Left-Justified Serial Audio Interface ............................................................................ 17

Figure 20. I2S Serial Audio Interface ............................................................................................ 17

Figure 21. CS5342 Recommended Analog Input Buffer .............................................................. 18

Figure 22. CS5342 THD+N versus Frequency ............................................................................ 19

LIST OF TABLES

Table 1. Speed Modes and the Associated Output Sample Rates (Fs)........................................ 15

Table 2. CS5342 Mode Control..................................................................................................... 15

Table 3. Master Clock (MCLK) Ratios........................................................................................... 17

Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates .......................... 17

Table 5. Revision History .............................................................................................................. 22