CS42436 datasheet(35/66 Pages) CIRRUS

35 / 66 page

DS647PP2

FS is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data

sample and must be held valid for at least 1 SCLK period.

NOTE: The ADC does not meet the timing requirements for proper operation in Quad-Speed

Mode.

5.5.2 I/O Channel Allocation

Digital

Input/Output

Interface

Format

Analog Output/Input Channel Allocation

from/to Digital I/O

DAC_SDIN

TDM

AOUT 1,2,3,4,5,6

ADC_SDOUT

TDM

AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN)

Table 6. Serial Audio Interface Channel Allocations

SCLK

256 clks

Bit or Word Wide

AOUT6

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

DAC_SDIN

AOUT1

AOUT4

AOUT2

AOUT5

AOUT3

32 clks

LSB

MSB

LSB

MSB

32 clks

MSB

LSB

AIN6

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

ADC_SDOUT

AIN1

AIN4

AIN2

AIN5

AIN3

32 clks

AUX2

LSB

MSB

LSB

MSB

AUX1

32 clks

MSB

Figure 14. TDM Serial Audio Format

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