X4323 datasheet(13/21 Pages) INTERSIL

13 / 21 page

FN8122.0

March 29, 2005

Figure 15. X4323/5 Addressing

Operational Notes

The device powers-up in the following state:

– The device is in the low power standby state.

– The WEL bit is set to ‘0’. In this state it is not possi-

ble to write to the device.

– SDA pin is the input mode.

– RESET Signal is active for tPURST.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– The WEL bit must be set to allow write operations.

–The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile

write cycle.

– A three step sequence is required before writing into

the Control Register to change Watchdog Timer or

Block Lock settings.

– The WP pin, when held HIGH, and WPEN bit at logic

HIGH will prevent all writes to the Control Register.

– Communication to the device is inhibited while

RESET/RESET is active and any in-progress com-

munication is terminated.

– Block Lock bits can protect sections of the memory

array from write operations.

SYMBOL TABLE

R/W

Slave Address Byte

Device Identifier

Device Select

A10

A11

Word Address Byte 0–32K

High Order Word Address

(X5)

(X4)

(X3)

(X2)

Word Address Byte 0 for all options

Low Order Word Address

(Y2)

(Y1)

(Y0)

(Y3)

(Y4)

(Y5)

(X0)

(X1)

Data Byte for all options

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

X4323, X4325

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