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DSPA56371 Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc |
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DSPA56371 Datasheet(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 124 page  Serial Host Interface SPI Protocol Timing Freescale Semiconductor DSP56371 Technical Data 39 12 Serial Host Interface SPI Protocol Timing Table 20. Serial Host Interface SPI Protocol Timing No. Characteristics1 Mode Min Max Unit 23 Minimum serial clock cycle = tSPICC(min) Master 79.0 — ns 24 Serial clock high period Master 29.5 — ns Slave 25.8 — ns 25 Serial clock low period Master 29.5 — ns Slave 25.8 — ns 26 Serial clock rise/fall time Master — 10 ns Slave — 10 ns 27 SS assertion to first SCK edge CPHA = 0 Slave 34.4 — ns CPHA = 1 Slave 10 — ns 28 Last SCK edge to SS not asserted Slave 12 — ns 29 Data input valid to SCK edge (data input set-up time) Master/Slave 0 — ns 30 SCK last sampling edge to data input not valid Master/Slave 22.4 — ns 31 SS assertion to data out active Slave 5 — ns 32 SS deassertion to data high impedance2 Slave — 9 ns 33 SCK edge to data out valid (data out delay time) Master/Slave — 100 ns 34 SCK edge to data out not valid (data out hold time) Master/Slave 21.4 — ns 35 SS assertion to data out valid (CPHA = 0) Slave — 15.0 ns 36 First SCK sampling edge to HREQ output deassertion Slave 50 — ns 37 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave 52.2 — ns 38 SS deassertion to HREQ output not deasserted (CPHA = 0) Slave 46.6 — ns 39 SS deassertion pulse width (CPHA = 0) Slave 12.7 — ns 40 HREQ in assertion to first SCK edge Master — — ns 41 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) Master 0 — ns 42 First SCK edge to HREQ in not asserted (HREQ in hold time) Master 0 — ns 43 HREQ assertion width Master ns Notes: 1. VCORE_VDD = 1.2 5 ± 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF 2. Periodically sampled, not 100% tested |
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