PD

1 µA

To

amplifier

core

VS+

GND

THP210

Enabled

MOSFET

THRESHOLD

Powerdown

12

THP210

SBOS932 – FEBRUARY 2020

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Product Folder Links: THP210

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Most applications for the THP210 strive to deliver the best dynamic range in a design that delivers the desired

signal processing along with adequate phase margin for the amplifier itself. The following sections detail some of

the design issues with analysis and guidelines for improved performance.

8.1.1 Driving Capacitive Loads

The capacitive load of an ADC or some other next-stage device is commonly required to be driven. Directly

connecting a capacitive load to the output pins of a closed-loop amplifier such as the THP210 can lead to an

0-Ω value initially) for later adjustment, in case the response appears unacceptable.

8.1.2 Operating the Power-Down Feature

The power-down feature on the THP210 allows the device to be put into a low power-consumption state, in

which quiescent current is minimized. To force the device into the low-power state, drive the PD pin to less than

to disable both the differential and common-mode amplifiers. The PD pin has an internal pullup current that

allows for the pin to be used in an open-drain MOSFET configuration without an additional pullup resistor, as

seen in Figure 12. In this configuration, the logic level can be referenced to the MOSFET, and the voltage at the

PD pin is level-shifted to account for use with high supply voltages. Be sure to select an N-type MOSFET with a

Figure 12. Power-Down (PD) Pin Interface With Low-Voltage Logic Level Signals

For applications that do not use the power-down feature, tie the PD pin to the positive supply voltage.

When PD is low (device is in power down) the output pins will be in a high-impedance state.