UCD8220PWPR datasheet(19/32 Pages) TI

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OUT

RAMP*

CTRL

CLF

CLK

UVLO and

REF OK*

* - Internal signals

PWM*

Start up

Steady State

Current Limit

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

Figure 39. UCD8220 and UCD8620 Timing and Circuit Operation Diagram

to switch. The JFET remains off provided the outputs

JFET Operation (UCD8620 Only)

are switching and the VDD voltage stays above 7.5

The UCD8620 digitally managed push-pull analog

V. If the VDD voltage drops below 7.5 V while the

PWM Controller contains a 110-V start-up JFET to

outputs are switching, the outputs are immediately

simplify the start-up and standby power requirements

disabled, and the JFET is switched back on. It then

for systems with digital controllers. The JFET circuit

attempts to charge the VDD voltage back up to 13 V.

has two operating modes. When the VDD voltage is

Once the VDD voltage reaches 13 V, the outputs are

less than 5 V, the circuit is limited to 5 mA of source

enabled again and allowed to switch. If the CLK input

current into VDD. The VDD reaches 5 V, the circuit

is not switched by the digital controller, then the VDD

switches into temperature protection mode and pro-

voltage decays to 12 V, and the JFET turns on again.

vides 10 mA until the temperature of the die exceeds

This charges the VDD capacitor back to 13 V where

145

°C. Figure 40 shows the operation of the JET

the cycle repeats until the input voltage drops to a

circuitry

during

various

operating

conditions.

point where the VDD voltage can no longer be

start-up, the JFET is on and charges up the VDD

maintained. Figure 41 shows the graph of available

capacitor. Once the VDD voltage reaches its UVLO of

source current as a function of input and VDD

13 V, the JFET turns off and the outputs are allowed

voltage.

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