9

Applications Information

Video In

A simplified block diagram is shown in Figure 6.

nominally 0.1µF. Clamp charge current will prevent the

signal on pin 2 from going any more negative than Sync Tip

Ref, about 1.5V. This charge current is nominally about

1mA. A clamp discharge current of about 10µA is always

lost between sync pulses that must be replaced during sync

pulses. The droop voltage that will occur can be calculated

from IT = CV, where V is the droop voltage, I is the discharge

current, T is the time between sync pulses (sync period -

An NTSC video signal has a horizontal frequency of

15.73kHz, and a sync tip width of 4.7µs. This gives a period

of 63.6µs and a time T = 58.9µs. The droop voltage will then

be V = 5.9mV. This is less than 2% of a nominal sync tip

amplitude of 286mV. The charge represented by this droop

is replaced in a time given by T=CV/I, where I = clamp

charge current = 1mA. Here T = 590ns, about 12% of the

enough so that the droop voltage does not approach the

50% switching threshold of the internal comparator.

AGC and Composite Sync

The clamped video signal then passes to the AGC, which

will maintain the blanking level of its output (sensed during

burst) at the blanking reference level. The AGC should

therefore present a constant amplitude signal to the

comparator, if the input is within the AGC's dynamic range. A

50% slicing reference is compared with the AGC's output at

the comp circuit. Comp's output is level shifted and buffered

to TTL levels, and sent out as Comp Sync on pin 1.

Burst

A low-going Burst pulse follows each rising edge of sync,

signal is used internally to gate the AGC feedback for

determining blanking level.

Vertical Sync

A low-going Vertical Sync pulse is output during the start of

the vertical cycle of the incoming video signal. The vertical

cycle starts with a pre-equalizing phase of pulses with a duty

cycle of about 93%, followed by a vertical serration phase

that has a duty cycle of about 15%. Vertical Sync is clocked

out of the EL1882C on the first rising edge during the vertical

serration phase. In the absence of vertical serration pulses,

a vertical sync pulse will be forced out after the vertical sync

FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL

EL1882C