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SL2S1502 Datasheet(PDF) 10 Page - NXP Semiconductors |
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SL2S1502 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 33 page ![]() NXP Semiconductors SL2S1402_SL2S1502_SL2S1602 ICODE ILT SL2S1402_SL2S1502_SL2S1602 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 3.3 — 15 October 2019 COMPANY PUBLIC 234333 10 / 33 Type sandwich structure Material PE-nitride (on top) Thickness 1.75 μm total thickness of passivation Au bump Material >99.9 % pure Au Hardness 35 HV to 80 HV 0.005 Shear strength >70 MPa Height 18 μm Height uniformity within a die ±2 μm within a wafer ±3 μm wafer to wafer ±4 μm Bump flatness ±1.5 μm Bump size LA, LB 60 μm × 60 μm TEST, GND 60 μm × 60 μm variation ±5 μm Under bump metallization sputtered TiW 8.1.1 Fail die identification No inkdots are applied to the wafer. Electronic wafer mapping (SECS II format) covers the electrical test results and additionally the results of mechanical/visual inspection. See Ref. 13 "General specification for 8" wafer on UV-tape with electronic fail die marking" 8.1.2 Map file distribution See Ref. 13 "General specification for 8" wafer on UV-tape with electronic fail die marking". |
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