TSC51C1 datasheet(13/31 Pages) TEMIC

13 / 31 page

TSC8051C1

Rev. D (14 Jan. 97)

MATRA MHS

Order

Source

Priority Within Level

INT0

(highest)

Timer 0

↑

INT1

Timer 1

SIO0

↓

SIO1

(lowest)

6.8.3. Interrupt Handling:

The interrupt flags are sampled at S5P2 of every

machine cycle. The samples are polled during the

following machine cycle. If one of the flags was in a set

condition at S5P2 of the previous machine cycle, the

polling cycle will find it and the interrupt system will

generate a LCALL to the appropriate service routine,

provided this hardware–generated LCALL is not

blocked by any of the following conditions:

1. An interrupt of higher or equal priority is

already in progress.

2. The current (polling) cycle is not the final

cycle in the execution of the instruction in progress.

3. The instruction in progress is RETI or any

access to the IE or IP SFR.

Any of these three conditions will block the generation

of the LCALL to the interrupt service routine. Note that

if an interrupt is active but not being responded to for one

of the above conditions, if the flag is not still active when

the blocking condition is removed, the denied interrupt

will not be serviced. In other words, the facts that the

interrupt flag was once active but not serviced is not

memorized. Every polling cycle is new.

The processor acknowledges an interrupt request by

executing

hardware–generated

LCALL

the

appropriate service routine. In some cases it also clears

the flag that generated the interrupt, and in other case it

does not. It clears the timer 0, timer 1, and external

interrupt flags. An external interrupt flag (IE0 or IE1) is

cleared only if it was transition–activated. All other

interrupt flags are not cleared by hardware and must be

cleared by the software. The LCALL pushes the

contents of the program counter onto the stack (but it

does not save the PSW) and reloads the PC with an

address that depends on the source of the interrupt being

vectored to, as listed below:

Source

Vector Address

IE0

0003h

TF0

000Bh

IE1

0013h

TF1

001Bh

RI + TI

0023h

002Bh

Execution proceeds from the vector address until the

RETI instruction is encountered. The RETI instruction

clears the ‘priority level active’ flip–flop that was set

when this interrupt was acknowledged. It then pops two

bytes from the the top of the stack and reloads the

program counter with them. Execution of the interrupted

program continues from where it was interrupted.

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