MMA6525KW datasheet(49/56 Pages) NXP

49 / 56 page

Sensor

Freescale Semiconductor, Inc.

MMA65xx

4.4

Two types of register access operations are supported; register write, and register read. Register access operations are initi-

ated when the acceleration bit (A) of the command message is set to a logic ‘0’. The operation to be performed is indicated by

the Access Selection bit (AX) of the command message.

Register Access operations include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the Register Access

operation must be an odd number.

4.4.1

During a register write request, bits 12 through 8 contain a five-bit address, and bits 7 through 0 contain the data value to be

written. Writable registers are defined in Table 3.

The response to a register write operation is shown in Table 30. The response is transmitted on the next SPI message if and

only if all of the following conditions are met:

•

No SPI Error is detected (Reference Section 4.5.1)

•

No MISO Error is detected (Reference Section 4.5.2)

•

The ENDINIT bit is cleared (Reference Section 3.1.6.3)

– This applies to all registers with the exception of the DEVCTL register (Only Bits 6 and 7 can be modified)

•

No Invalid Register Request is detected (Reference Section 4.5.3.2)

If the above conditions are met, the device responds to the register write request as shown in Table 30. Otherwise, the device

Responds as specified in Section 4.5.

Register write operations do not occur internally until the transfer during which they are requested has been completed. In the

event that a SPI Error is detected during a register write transfer, the write operation is not completed.

4.4.2

During a register read request, bits 12 through 8 contain the five-bit address for the register to be read. Bits 7 through 0 must

be logic ‘0’. Readable registers are defined in Table 3.

The response to a register read operation is shown in Table 30. The response is transmitted on the next SPI message if and

only if all of the following conditions are met:

•

No SPI Error is detected (Reference Section 4.5.1)

•

No MISO Error is detected (Reference Section 4.5.2)

•

No Invalid Register Request is detected (Reference Section 4.5.3.2)

If the above conditions are met, the device responds to the register read request as shown in Table 30. Otherwise, the device

responds as specified in Section 4.5.

Access Selection Bit (AX)

Operation

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