Am79D2251

27

PCM Interface

Master Clock

For 2.048 MHz ±100 PPM, 4.096 MHz ±100 PPM, or 8.192 MHz ±100 PPM operation:

Notes:

1.

DCLK may be stopped in the HIGH or LOW state indefinitely without loss of information. When CS

makes a transition to the High state, the last byte received will be interpreted by the Microprocessor

Interface logic.

2.

The PCM clock (PCLK or MCLK) frequency must be an integer multiple of the frame sync (FS)

frequency with an accuracy of 100 PPM. This allowance includes any jitter that may occur between

the PCM signals (FS, PCLK) and MCLK. The actual PCLK rate is dependent on the number of channels

allocated within a frame. The minimum clock frequency is 128 kHz. A PCLK of 1.544 MHz may be

used for standard U.S. transmission systems.

3.

slot register.

4.

the load circuitry. The maximum load capacitance on TSCA is 150 pF and the minimum pull-up

resistance is 360

Ω.

5.

The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs

last.

6.

The ISLAC device requires 2.0

µs between SIO operations. If the MPI is being accessed while the

MCLK (or PCLK if combined with MCLK) input is not active, a Chip Select Off time of 20

µs is required

when accessing coefficient RAM.

No.

Symbol

Parameter

Min.

Typ

Max

Unit

Note

22

PCM clock period

0.122

7.8125

µs

2

23

PCM clock HIGH pulse width

48

ns

24

PCM clock LOW pulse width

48

25

Fall time of clock

15

26

Rise time of clock

15

27

FS setup time

30

28

FS hold time

50

29

Delay to TSCA valid

5

80

3

30

Delay to TSCA off

5

4

31

PCM data output delay

5

70

32

PCM data output hold time

5

70

33

PCM data output delay to high-Z

10

70

34

PCM data input setup time

25

35

PCM data input hold time

5

36

PCM or frame sync jitter time

–97

97

No.

Symbol

Parameter

Min

Typ

Max

Unit

No

37

Period: 2.048 MHz

Period: 4.096 MHz

Period: 8.192 MHz

488.23

244.11

122.05

488.28

244.14

122.07

488.33

244.17

122.09

ns

2

38

Rise time of clock

15

39

Fall time of clock

15

40

MCLK HIGH pulse width

48

41

MCLK LOW pulse width

48