IR21771S datasheet(13/16 Pages) IRF

13 / 16 page

IR22771S/IR21771S(PbF)

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For this particular PWM scheme another suitable

solution is driving the IR2x771 with a half frequency

SYNC signal (fSYNC=fPWM/2).

In this case the cut frequency of the input filter is

reduced by half allowing zeroes to be put at fPWM

multiples (i.e. even and odd harmonics cancellation,

no more computational effort needed by the

controller).

Figure 15: Even harmonic cancellation principle

1.6 Input filter gain setting

G0 and G1 pins are used to change the time

constant of the integrators of the high side input

filter.

To avoid internal saturation of the input filter, G0

and G1 must be connected according to SYNC

frequency as shown in Table 1. A too small time

constant may saturate the internal integrator, while

a large time constant may reduce accuracy.

G0 and G1 do not affect the overall current sensor

gain.

f PWM

> 16 kHz *

16 / 10 kHz

10 / 6 kHz

< 6 kHz

40 kHz

Table 1: G0, G1 gain settings

Triangular

Phase voltage

Phase current

Current Mean

Fundamental

harmonic

Fundamental

harmonic

Switching level

Third

harmonic

Third

harmonic

SYNC 1

SYNC 2

Sampling

instant

Sampling

instant

Error

Triangular

Phase voltage

Phase current

Current Mean

Fundamental

harmonic

Fundamental

harmonic

Switching level

Third

harmonic

Stage 1 input:

Input signal

components

st and 2nd

harmonic only)

Third

harmonic

SYNC 1

SYNC 2

Sampling

instant

Sampling

instant

Error

Stage 1

output

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