TMCS1101 datasheet(6/48 Pages) TI1

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TMCS1101

SBOS825A – SEPTEMBER 2019 – REVISED MAY 2020

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(1)

Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care to

maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the printed-

circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques

such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2)

Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(3)

Apparent charge is electrical discharge caused by a partial discharge (pd).

(4)

All pins on each side of the barrier tied together creating a two-terminal device

7.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

UNIT

GENERAL

CLR

External clearance(1)

Shortest terminal-to-terminal distance through air

CPG

External creepage(1)

Shortest terminal-to-terminal distance across the package

surface

DTI

Distance through the insulation

Minimum internal gap (internal clearance)

µm

CTI

Comparative tracking index

DIN EN 60112; IEC 60112

>400

Material group

Overvoltage category

Rated mains voltage

≤ 150 VRMS

I-IV

Rated mains voltage

≤ 300 VRMS

I-III

VIORM

Maximum repetitive peak isolation voltage

AC voltage (bipolar)

600

VPK

VIOWM

Maximum working isolation voltage

AC voltage (sine wave); Time Dependent Dielectric

Breakdown test, see Figure 31

424

VRMS

DC voltage

600

VDC

VIOTM

Maximum transient isolation voltage

VTEST = VIOTM = 4242VPK, t = 60 s (qualification);

VTEST = 1.2 × VIOTM = 5090VPK, t = 1 s (100% production)

4242

VPK

VIOSM

Maximum surge isolation voltage(2)

Test method per IEC 62368-1, 1.2/50 µs waveform,

VTEST = 1.3 × VIOSM = 7800VPK (qualification)

6000

VPK

qpd

Apparent charge(3)

Method a: After I/O safety test subgroup 2/3,

Vini = VIOTM = 4242VPK, tini = 60 s;

Vpd(m) = 1.2 × VIORM = 700VPK, tm = 10 s

≤5

Method a: After environmental tests subgroup 1,

Vini = VIOTM = 4242VPK, tini = 60 s;

Vpd(m) = 1.2 × VIORM = 700VPK, tm = 10 s

≤5

Method b3: At routine test (100% production) and

preconditioning (type test)

Vini = 1.2 × VIOTM = 5090VPK, tini = 1 s;

Vpd(m) = 1.2 × VIOTM = 5090VPK, tm = 1 s

≤5

CIO

Barrier capacitance, input to output(4)

VIO = 0.4 sin (2πft), f = 1 MHz

0.6

RIO

Isolation resistance, input to output(4)

VIO = 500 V, TA = 25°C

>1012

Ω

VIO = 500 V, 100°C ≤ TA ≤ 125°C

>1011

Ω

VIO = 500 V at TS = 150°C

>109

Ω

Pollution degree

UL 1577

VISO

Withstand isolation voltage

VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO,

t = 1 s (100% production)

3000

VRMS

7.7 Safety-Related Certifications

Pending recognition under UL 1577 Component Recognition

Program

Pending certification according to IEC 62368-1 CB

File number: Pending

Client ID number: Pending

TMCS1101 Datasheet(PDF) 6 Page - Texas Instruments

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