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XRT7250 Datasheet(PDF) 146 Page - Exar Corporation |
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XRT7250 Datasheet(HTML) 146 Page - Exar Corporation |
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146 / 463 page ![]() áç áç áç áç DS3/E3 FRAMER IC XRT7250 REV. 1.1.1 127 XRT7250 CONFIGURATION The XRT7250 DS3/E3 Framer IC can be configured to support any of the following four framing formats. • DS3/C-Bit Parity • DS3/M13 • E3/ITU-T G.832 • E3/ITU-T G.751 As a consequence, the discussion of the XRT7250 Framer IC will be organized as follows: Section 4.0 - DS3 Mode Operation of the XRT7250 Section 5.0 - E3, ITU-T G.751 Operation of the XRT7250 Section 6.0 - E3, ITU-T G.832 Operation of the XRT7250 Section 6.0 - Framer Local Loop-back Mode Opera- tion 4.0 DS3 OPERATION OF THE XRT7250 This section will discuss in detail, the operation of the XRT7250 Framer IC, when it has been configured to operate in the DS3 Mode. Configuring the XRT7250 to Operate in the DS3 Mode The XRT7250 can be configured to operate in the DS3 Mode by writing a "1" into bit-field 6 within the Framer Operating Mode register, as illustrated below. Prior to describing the functional blocks within the Transmit and Receive Sections of the XRT7250, it is important to describe the following two framing for- mats. • M13 • C-Bit Parity 4.1 DESCRIPTION OF THE DS3 FRAMES AND ASSOCI- ATED OVERHEAD BITS The role of the various overhead bits are best de- scribed by discussing the DS3 Frame Format as a whole. The DS3 Frame contains 4760 bits, of which 56 bits are overhead and the remaining 4704 bits are payload bits. The payload data is formatted into packets of 84 bits and the overhead (OH) bits are in- serted between these payload packets. The XRT7250 Framer supports the following two DS3 framing formats: • C-bit Parity • M13 Figures 40 and 41 present the DS3 Frame Format for C-bit Parity and M13, respectively. X = Signaling bit for network control I = Payload Information (84 bit packets) FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) BIT 7 BIT 6BIT 5BIT 4BIT 3BIT2BIT 1BIT 0 Local Loopback DS3/E3* Internal LOS Enable RESET Interrupt Enable Reset Frame Format TimRefSel[1:0] R/W R/W R/W R/W R/W R/W R/W R/W x 1x 0 x x x x FIGURE 40. DS3 FRAME FORMAT FOR C-BIT PARITY X IF1 IAIC IF0 INA IF0 I FEAC IF1 I I X IF1 I UDL IF0 INA IF0 I UDL IF1 I P IF1 ICP IF0 ICP IF0 ICP IF1 I P IF1 I FEBE IF0 I FEBE IF0 I FEBE IF1 I M0 IF1 IDL IF0 IDL IF0 IDL IF1 I M1 IF1 I UDL IF0 I UDL IF0 I UDL IF1 I M0 IF1 I UDL IF0 I UDL IF0 I UDL IF1 I |
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