XRT7250 datasheet(212/463 Pages) EXAR

212 / 463 page

áç

DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

193

The Receive DS3 Framer block is capable of detect-

ing any of the following alarm conditions.

• LOS (Loss of Signal)

• AIS (Alarm Indication Signal)

• The Idle Pattern.

• FERF (Far-End Receive Failure) of Yellow Alarm

condition.

• FEBE (Far-End-Block Error)

• Change in AIC State

The methods by which the Receive DS3 Framer block

uses to detect and declare each of these alarm condi-

tions are described below.

4.3.2.5.1

The Loss of Signal (LOS) Alarm

The Receive DS3 Framer block will declare a Loss of

Signal (LOS) state when it detects 180 consecutive

incoming 0s via the RxPOS and RxNEG input pins or

if the RLOS input pin (from the XRT7300 DS3 LIU or

the XRT7295 Line Receiver IC) is asserted (e.g., driv-

en "High"). The Receive DS3 Framer block will indi-

cate the occurrence of an LOS condition by:

1. Asserting the RxLOS output pin (e.g., toggles it

"High").

2. Setting Bit 6 (RxLOS) within the Rx DS3 Configu-

ration and Status Register to 1, as depicted

below.

3. The Receive DS3 Framer block will generate a

Change in LOS Status interrupt request.

NOTE: The Receive DS3 Framer will also declare an OOF

condition and perform all of the notification procedures as

described in Section 3.3.2.2.

4. Force the on-chip Transmit Section to transmit a

FERF (Far-End Receive Failure) indicator back

out to the remote terminal.

The Receive DS3 Framer block will clear the LOS

condition when at least 60 out of 180 consecutive re-

ceived bits are 1.

NOTE: The Receive DS3 Framer block will also generate

the Change in LOS Condition interrupt, when it clears the

LOS Condition.

The Framer chip allows the user to modify the LOS

Declaration criteria such that an LOS condition is de-

clared only if the RLOS input pin (from the XRT7300

DS3/E3/STS-1 LIU IC) is asserted. In this case, the

internally-generated LOS criteria of 180 consecutive

0s will be disabled. The user can accomplish this by

writing a "1" to bit 3 (Int LOS Disable) of the Rx DS3

Configuration and Status Register, as depicted below.

NOTE: For more information on the RLOS input pin, please

see Section 2.1.

4.3.2.5.2

The Alarm Indication Signal (AIS)

The Receive DS3 Framer block will identify and de-

clare an AIS condition if it detects all of the following

conditions in the incoming DS3 Data Stream:

• Valid M-bits, F-bits and P-bits

• All C-bits are zeros.

• X-bits are set to 1

• The Payload portion of the DS3 Frame exhibits a

repeating 1010... pattern.

The Receive DS3 Framer block contains, within its

circuitry, an Up/Down Counter that supports the as-

sertion and negation of the AIS condition. This

counter begins with the value of 0x00 upon power up

or reset. The counter is then incremented anytime

the Receive DS3 Framer block detects an AIS Type

M-frame. This counter is then decremented, or kept

at zero value, when the Receive DS3 Framer block

detects a non-AIS type M-frame. The Receive DS3

Framer block will declare an AIS Condition if this

counter reaches the value of 63 M-frames or greater.

Explained another way, the AIS condition is declared

RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)

BIT 7

BIT 6BIT 5BIT 4BIT 3BIT2BIT 1BIT 0

RxAIS

RxLOS

RxIdle

RxOOF

Int LOS

Disable

Framing on

Parity

F-Sync Algo

M-Sync Algo

R/O

R/W

101

RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)

BIT 7BIT 6BIT 5BIT 4

BIT 3BIT2BIT 1BIT 0

RxAIS

RxLOS

RxIdle

RxOOF

Int LOS

Disable

Framing on

Parity

F-Sync Algo

M-Sync Algo

R/W

XRT7250 Datasheet(PDF) 212 Page - Exar Corporation

XRT7250 Datasheet(HTML) 212 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL