XRT7250 datasheet(214/463 Pages) EXAR

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

195

2. Generate a Change in Idle Status Interrupt

Request to the local µP/µC.

The Receive DS3 Framer block will clear the Idle

Condition if it has detected a sufficient number of

Non-Idle M-frames, such that this Up/Down Counter

reaches the value 0.

4.3.2.5.4

The Detection of (FERF) or Yellow

Alarm Condition

The Receive DS3 Framer block will identify and de-

clare a Yellow Alarm condition or a Far-End Receive

Failure (FERF) condition, if it starts to receive DS3

frames with both of its X-bits set to 0.

When the Receive DS3 Framer block detects a FERF

condition in the incoming DS3 frames, then it will then

do the following.

1. It will assert the RxFERF (bit-field 4) within the

Rx DS3 Status Register, as depicted below.

This bit-field will remain asserted for the duration that

the Yellow Alarm condition exists.

2. The Receive DS3 Framer block will also generate

a Change in FERF Status interrupt to the µP/µC.

Consequently, the Receive DS3 Framer block will

also assert the FERF Interrupt Status bit, within

the Rx DS3 Interrupt Status Register, as depicted

below.

The Receive DS3 Framer block will clear the FERF

condition, when it starts to receive Receive DS3

Frames that have its X bits set to 1.

NOTE: The FERF indicator is frequently referred to as the

Yellow Alarm.

4.3.2.5.5

The Detection of the FEBE Events

As described in Section 3.2.4.2.1.9, a given Terminal

Equipment will set the three FEBE (Far-End Block Er-

ror) bit-fields to the value [1, 1, 1] (e.g., all of the

FEBE bits are set to “1”) within the outbound DS3

frames if, all of the following conditions are true about

the incoming DS3 line signal.

• The Receive Circuitry (within the Terminal Equip-

ment) detects no P-Bit Errors.

• The Receive Circuitry (within the Terminal Equip-

ment) detects no CP-Bit Errors.

If the Receive Section of the Terminal Equipment de-

tects any P or CP bit errors, then the Transmit Section

of the Terminal Equipment will set the three FEBE

bits (within the outbound DS3 data stream) to a value

other than [1, 1, 1].

How does the Receive DS3 Framer block (within the

XRT7250) respond when it receives a DS3 frame with

all three (3) of its FEBE bit-fields set to “1”?

As mentioned above, the Terminal Equipment will

transmit DS3 frames, with the FEBE bits set to [1, 1,

1], during un-erred conditions. Hence, if the Receive

DS3 Framer block (within the XRT7250 Framer IC)

receives DS3 frames with the FEBE bits set to [1, 1,

1] it will interpret this event as an un-erred event, and

will continue normal operation.

However, if the Receive DS3 Framer block receives a

DS3 frame with the FEBE bits set to a value other

than [1, 1, 1], then it will increment the PMON FEBE

Event Count Registers (which are located at address

locations 0x58 and 0x59 within the Framer Address

space).

4.3.2.5.6

Detection of Change in the AIC State

Section 3.1 indicates that the AIC (Application Identi-

fication Channel) bit-field is the third overhead bit,

within F-Frame # 1. This particular bit-field is set to

“1” for the C-Bit Parity Framing Format, and is set to

“0” for the M13 Framing Format.

RX DS3 STATUS REGISTER (ADDRESS = 0X11)

BIT 7BIT 6BIT 5

BIT 4BIT 3BIT2BIT 1BIT 0

Not Used

Rx FERF

RxAIC

RxFEBE [2]

RxFEBE [1]

RxFEBE [0]

RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)

BIT 7BIT 6BIT 5BIT 4

BIT 3BIT2BIT 1BIT 0

Cp Bit Error

Interrupt

Status

LOS Interrupt

Status

AIS Interrupt

Status

IDLE Interrupt

Status

FERF Inter-

rupt Status

AIC Interrupt

Status

OOF Interrupt

Status

P-Bit Interrupt

Status

RUR

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