XRT7250 datasheet(215/463 Pages) EXAR

215 / 463 page

XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

196

Hence, a given Terminal Equipment receiving a DS3

data stream can identify the framing format of this

DS3 data stream, by reading the value fo the AIC bit-

field. The Receive DS3 Framer block permits the us-

er’s Microcontroller/MIcroprocessor to determine the

state of the AIC bit-field (within the incoming DS3 da-

ta stream) by writing the value of the AIC bit-field,

within the most recently received DS3 frame, into bit

3 (RxAIC) within the Rx DS3 Status Register (Ad-

dress = 0x11), as illustrated below.

The Receive DS3 Framer block will also generate an

interrupt if it detects a change of state in the AIC bit-

field (within the incoming DS3 data stream). If this

occurs, then the Receive DS3 Framer block will set

Bit 2 (AIC Interrupt Status) within the Rx DS3 Inter-

rupt Stauts Register (Address = 0x13) to “1” as illus-

trated below.r

4.3.2.6

Performance Monitoring of the DS3

Transport Medium

The DS3 Frame consists of some overhead bits that

are used to support performance monitoring of the

DS3 Transmission Link. These bits are the P-Bits

and the CP-Bits.

4.3.2.6.1

P-Bit Checking/Options

The remote Transmit DS3 Framer will compute the

even parity of the payload portion of an outbound

DS3 Frame and will place the resulting parity bit value

in the 2 P-bit-fields within the very next outbound DS3

Frame. The value of these two bits fields is expected

to be the identical.

The Receive DS3 Framer block, while receiving each

of these DS3 Frames (from the remote Transmit DS3

Framer), will compute the even-parity of the payload

portion of the frame. The Receive DS3 Framer block

will then compare this locally computed parity value

to that of the P-bit fields within the very next DS3

Frame. If the Receive DS3 Framer block detects a

parity error, then two things will happen:

1. The Receive DS3 Framer block will inform the µP/

µC of this occurrence by generating a Detection

of P-Bit Error interrupt,

2. The Receive DS3 Framer block will alter the

value of the FEBE bits, (to a pattern other than

111) that the Near-End Transmit DS3 Framer will

be transmitting back to the remote Terminal.

3. The XRT7250 Framer IC will increment the

PMON Parity Error Event Count Registers

(Address = 0x54 and 0x55) for each detected

parity error, in the incoming DS3 data stream.

The bit-format of these two registers follows.

RXDS3 STATUS REGISTER (ADDRESS = 0X11)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Reserved

RxFERF

RxAIC

RxFEBE[2:0]

000

RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

CP-Bit Error

Interrupt

Status

LOS

Interrupt

Status

AIS

Interrupt

Status

Idle Interrupt

Status

FERF

Interrupt

Status

AIC

Interrupt

Status

OOF

Interrupt

Status

P-Bit Error

Interrupt

Status

RURRUR

RUR

RURRUR

000

100

PMON PARITY ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X54)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT2BIT 1BIT 0

Parity Error Count - High Byte

000

XRT7250 Datasheet(PDF) 215 Page - Exar Corporation

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