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TLE9461ES Datasheet(PDF) 137 Page - Infineon Technologies AG |
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TLE9461ES Datasheet(HTML) 137 Page - Infineon Technologies AG |
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137 / 140 page  Datasheet 137 Rev.1.1 2019-09-27 TLE9461ES Lite CAN SBC Family Application Information Figure 49 Board Setup Board setup is defined according JESD 51-2, -5, -7. Board: 75 x 75 x 1.5mm3 with 2 inner copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70µm). 14.4 Further Application Information • Please contact us for information regarding the pin FMEA • For further information you may contact http://www.infineon.com/ PCB (top view) PCB (bottom view) Detail SolderArea 70µm modelled (traces) 35µm, 90% metalization* 35µm, 90% metalization* 70µm / 5% metalization + cooling area *: means percentual Cu metalization on each layer Cross Section (JEDEC 1s0p) with Cooling Area Cross Section (JEDEC 2s2p) with Cooling Area PCB attached at Housing |
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