VSC7440 datasheet(289/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

272

•

Update frame check sequence (IFH.FWD.UPDATE_FCS):

If this injection IFH bit is set, the rewriter updates the FCS before forwarding a frame to the egress

port. By setting this bit in the Injection IFH, the internal CPU can leave it to switch core hardware to

make sure the FCS value included with the frame is correct even though no other frame

modifications are performed by the switch core.

•

Swap MACs (IFH.DST.ENCAP.SWAP_MAC):

Swap MACs in the Ethernet link layer and clear bit 40 of the new SMAC before sending the frame to

the egress port. Swapping the MACs will also force the frame FCS to be updated. Cannot be used if

IFH.FWD.DO_NOT_REW = 1.

3.27

Disassembler

This section provides information about the disassembler (DSM) block. The disassembler is mainly

responsible for disassembling cells into Taxi words and forwarding them to the port modules. In addition,

it has several other responsibilities such as:

•

MAC Control sublayer PAUSE function with generation of PAUSE frames and stop forwarding traffic

on reception of PAUSE frames

•

Aging of frames that are stopped by flow control

•

Controlling transmit data rate according to IEEE802.3ar

The following table lists replication terminology.

3.27.1

Setting Up Ports

In general, no additional configuration is required to bring up a port in the disassembler. However, the

following are some exceptions:

•

For the 10G capable ports, set DSM::BUF_CFG.CSC_STAT_DIS to 1 when the port is set up for

10 Gbps, because the collection of statistics are handled locally in the DEV10G. For lower speeds,

the port uses a DEV2G5.

•

For 10G capable ports, set DSM::DEV_TX_STOP_WM_CFG.DEV_TX_STOP_WM to 3 if the port is

set up for 2.5 Gbps or 1 Gbps, and set it to 1 for 100 Mbps and 10 Mbps.

•

For 10G capable ports, set DSM::DEV_TX_STOP_WM_CFG.DEV10G_SHADOW_ENA to 1 when

port is set up for speeds below 10 Gbps.

•

For 2.5G capable ports, the DSM::DEV_TX_STOP_WM_CFG.DEV_TX_STOP_WM must be set to

1 if the port is set up for 100 Mbps and 10 Mbps.

Ports are indexed by 0 – 10 being front ports and 11 – 12 being CPU ports.

The following table lists the registers associated with setting up basic ports.

Table 192 •

Replication Terminology

Replication Terminology Description

Replication Value

Per port

Per physical ports. For example, DEV1Gs,

DEV2G5s, DEV10Gs and CPU ports.

Table 193 •

Basic Port Setup Configuration Registers Overview

Target::Register.Field

Description

Replication

DSM::BUF_CFG.CSC_STAT_DIS

Disables collection of statistics in the disassembler.

Per port

DSM::DEV_TX_STOP_WM_CFG.DEV_TX

_STOP_WM

Watermark for maximum fill level of port module TX buffer. Per port

DSM::DEV_TX_STOP_WM_CFG.DEV10G

_SHADOW_ENA

Enable low speeds for 10G capable ports.

Per port

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