VSC7440 datasheet(291/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

274

3.27.3.2 Reaction on Received PAUSE Frame

The assembler detects received PAUSE frames and forwards the pause_time to the disassembler, which

stops data transmission (if enabled) for the period defined by pause_time. If PFC is enabled for a port,

then RX_PAUSE_EN must be disabled in the disassembler.

The following table lists the registers associated with configuring PAUSE frame reception.

3.27.3.3 PFC Pause Frame Generation

When PFC is enabled for a port, PFC PAUSE frames are generated when requested by the queue

system.

PFC is enabled on a per port basis in the disassembler. The queue system must also be setup to

generate PFC requests towards the disassembler. Regular flow control and PFC cannot operate

simultaneously on the same port. The available PFC configurations in the disassembler are listed in the

following table.

3.27.4

Setting up Flow Control in Half-Duplex Mode

The following table lists the configuration registers for half-duplex mode flow control. For more

information about setting up flow control in half-duplex mode, see PAUSE Frame Generation, page 273.

To enable half-duplex flow control, DSM::MAC_CFG.HDX_BACKPRESSURE must be set to 1. In this

mode, the disassembler forwards the FC status to the port modules, which then collides incoming

frames.

3.27.5

Setting Up Frame Aging

The following tables provide the aging configuration and status register settings. If frame aging is

enabled, the disassembler discards frames that are stuck, for example, due to flow control or frames that

Table 196 •

PAUSE Frame Reception Configuration Registers Overview

Target::Register.Field

Description

Replication

DSM::RX_PAUSE_CFG.RX_PAUSE_EN

Enables flow control in Rx direction

Per port

Table 197 •

PFC PAUSE Frame Generation Configuration Registers Overview

Target::Register.Field

Description

Replication

DSM::ETH_PFC_CFG.PFC_MIN_

UPDATE_TIME

Minimum time between two PFC PDUs when PFC state changes

after transmission of PFC PDU.

Per port

DSM::ETH_PFC_CFG.PFC_XOFF

_MIN_UPDATE_ENA

After sending PFC PDU with flow control deasserted for all

priorities, enforces a PFC_MIN_UPDATE_TIME delay before

allowing transmission of next PFC PDU.

Per port

DSM::ETH_PFC_CFG.PFC_ENA

Enables PFC operation for the port.

Per port

Table 198 •

Half-Duplex Mode Flow Control Configuration Register Overview

Target::Register.Field

Description

Replication

DSM::MAC_CFG.HDX_BACKPRESSURE

Enables HDX backpressure instead of FDX FC when FC

is generated.

Per port

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