VSC7440 datasheet(295/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

278

It is possible to recover receive timing from any 10/100/1000 Mbps, 2.5 Gbps, or SFI data streams into

the device.

The recovered clock outputs have individual divider configuration (through

SYNC_ETH_CFG.SEL_RCVRD_CLK_DIV) to allow division of SerDes receive frequency by 1, 2, 4, 5, 8,

16, or 25. In addition to the output dividers, the SFI 10G sources have local pre-dividers to allow

adjustments for the SFI links 64/66 encoding overhead by extending clock cycles through

SYNC_ETH_SD10G_CFG.SD10G_RCVRD_CLK_DIV.

The recovered clocks are single-ended outputs, and the suggested divider settings in the following tables

are selected to make sure to not output too high a frequency via the input and outputs.

Ports operating in 1 Gbps or lower speeds allow recovery of either 31.25 MHz or 125 MHz clocks.

Configure the ports as shown in the following table.

HSIO::PLL5G_CFG3

Enables high speed clock output.

PHY[0]:PHY_GP:PHY_RCVD_CLK0_CTRL

Configures PHY0 recovered clock.

PHY[1]:PHY_GP:PHY_RCVD_CLK1_CTRL

Configuration PHY1 recovered clock.

Table 207 •

Layer 1 Timing Recovered Clock Pins

Pin Name

I/O

Description

RCVRD_CLK0

Recovered clock output, configured by SYNC_ETH_CFG[0].

This is an overlaid function on GPIO.

RCVRD_CLK1

Recovered clock output, configured by SYNC_ETH_CFG[1].

This is an overlaid function on GPIO.

RCVRD_CLK2

Recovered clock output, configured by SYNC_ETH_CFG[2].

This is an overlaid function on GPIO.

RCVRD_CLK3

Recovered clock output, configured by SYNC_ETH_CFG[3].

This is an overlaid function on GPIO.

CLKOUTPLL

PLL high speed clock output.

CLKOUTPLL2

PLL2 high speed clock output.

Table 208 •

Recovered Clock Settings for 1 Gbps or Lower

Port

Output Frequency

CuPHY

0-1

125 MHz

Only for internal clocks (n = 4, 5, 6, and 7).

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=6,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV),

PHY_RCVD_CLK[DEV]_CTRL.RCVD_CLK[DEV]_ENA=1,

PHY_RCVD_CLK[DEV]_CTRL.CLK_SRC_SEL[DEV]=[DEV],

PHY_RCVD_CLK[DEV]_CTRL.CLK_FREQ_SEL[DEV]=1, and

PHY_RCVD_CLK[DEV]_CTRL.CLK_SEL_PHY[DEV]=1

Table 206 •

Layer 1 Timing Configuration Registers (continued)

Description

VSC7440 Datasheet(PDF) 295 Page - Microsemi Corporation

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