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VSC7440 Datasheet(PDF) 298 Page - Microsemi Corporation |
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VSC7440 Datasheet(HTML) 298 Page - Microsemi Corporation |
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298 / 444 page ![]() Functional Descriptions VMDS-10492 VSC7440 Datasheet Revision 4.2 281 The following table lists how to configure squelch for possible recovered clock sources (configured in SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC). When squelching, the clock will stop when it detects a loss of signal (or PLL lock). The clock will stop on either on high or low level. 3.29 Hardware Time Stamping Hardware time stamping provides nanosecond-accurate frame arrival and departure time stamps, which are used to obtain high precision timing synchronization and timing distribution, as well as significantly better accuracy in performance monitoring measurements than what is obtained from pure software implementations. The hardware time stamping functions operate in both standalone devices and in systems where multiple devices are interconnected to form a multichip system. Figure 83 • Supported Time Stamping Flows Hardware time stamping can update PTP frames coming from a standard front port without any 1588 support or from a partner device that does parts of the timing update. Each port is configured according to the partner device attached. Table 212 • Squelch Configuration for Sources SRC Associated Squelch Configuration 4-8 Set SERDES1G_COMMON_CFG.SE_AUTO_SQUELCH_ENA in SD macro to enable squelch when receive signal is lost. SD1G macro index is (SRC-4). 9-10 Set SERDES6G_COMMON_CFG.SE_AUTO_SQUELCH_ENA in SD macro to enable squelch when receive signal is lost. SD6G macro-index is (SRC-9). 14-17 Set SYNC_ETH_SD10G_CFG[(SRC-14)].SD10G_AUTO_SQUELCH_ENA to enable squelch when receive signal is lost. 12 Set SYNC_ETH_PLL_CFG[0].PLL_AUTO_SQUELCH_ENA to enable squelch when PLL loses lock. 21 Set SYNC_ETH_PLL_CFG[1].PLL_AUTO_SQUELCH_ENA to enable squelch when PLL2 loses lock. 1588-enabled Switch or PHY Device Interconnect Interconnect Front Port Front Port 1588-enabled Switch or PHY |
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