VSC7440 datasheet(297/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

280

clock cycle by half a clock-period. While this introduces jitter, it makes the frequency compatible with the

other recovered clocks. Configure as described in the following table.

The frequency of the PLLs can be used as recovered clock. The following table shows the configurations.

The recovered clock from PLLs can also be sent directly out on the differential high-speed CLKOUTPLL

and CLKOUTPLL2 outputs. The recovered clock frequency must be set to copy the switch core using

HSIO::PLL5G_CFG3.CLKOUT2_SEL.

It is possible to automatically squelch the clock output when the device detects a loss of signal on an

incoming data stream. This can be used for failover in external timing recovery solutions.

Table 210 •

Recovered Clock Settings for SFI

Port

Output Frequency

9-10

~161 MHz

(10.3125 GHz/64)

Only for internal clocks (n = 4, 5, 6, or 7).

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=0,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+6), and

SYNC_ETH_SD10G_CFG[DEV-7].SD10G_RCVRD_CLK_DIV=1.

9-10

156.25 MHz

Only for internal clocks (n = 4, 5, 6, or 7).

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=0,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+6), and

SYNC_ETH_SD10G_CFG[DEV-7].SD10G_RCVRD_CLK_DIV=2.

Synthesized by extending every 16th clock cycle by 1/2 period.

9-10

~32 MHz

(10.3125 GHz/320)

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=4,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+6), and

SYNC_ETH_SD10G_CFG[DEV-7].SD10G_RCVRD_CLK_DIV=1.

9-10

31.25 MHz

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=4,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+6), and

SYNC_ETH_SD10G_CFG[DEV-7].SD10G_RCVRD_CLK_DIV=2

Synthesized by extending (approximately) every third clock cycle by

1/10th period.

Table 211 •

Recovered Clock Settings for PLL

PLL

Output Frequency

PLL

125 MHz

Only for internal clocks (n = 4, 5, 6, or 7).

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=6, and

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=12

PLL

31.25 MHz

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=1, and

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=12

PLL2

125 MHz

Only for internal clocks (n = 4, 5, 6, or 7).

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=6, and

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=21

PLL2

31.25 MHz

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=1, and

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=21

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