VSC7440 datasheet(296/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

279

Ports operating in 2.5 Gbps mode allow recovery of a 31.25 MHz clock. The following table shows the

configuration settings.

Ports operating in SFI mode allow two base frequencies: One derived directly from the line rate, and one

that is adjusted for the 64/66 encoding overhead. The latter is generated by extending every sixteenth

CuPHY

0-1

31.25 MHz

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV),

PHY_RCVD_CLK[DEV]_CTRL.RCVD_CLK[DEV]_ENA=1,

PHY_RCVD_CLK[DEV]_CTRL.CLK_SRC_SEL[DEV]=[DEV],

PHY_RCVD_CLK[DEV]_CTRL.CLK_FREQ_SEL[DEV]=1, and

PHY_RCVD_CLK[DEV]_CTRL.CLK_SEL_PHY[DEV]=1

SerDes

0-6

125 MHz

Only for internal clocks (n = 4, 5, 6, and 7).

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=6, and

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+4)

SerDes

0-6

31.25 MHz

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=1, and

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+4)

7-10

125 MHz

Only for internal clocks (n = 4, 5, 6, and 7).

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=6,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+6), and

SYNC_ETH_SD10G_CFG[DEV-7].SD10G_RCVRD_CLK_DIV=0

7-10

31.25 MHz

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+6), and

SYNC_ETH_SD10G_CFG[DEV-7].SD10G_RCVRD_CLK_DIV=0

Table 209 •

Recovered Clock Settings for 2.5 Gbps

Port

Output Frequency

5-6

125 MHz

Only for internal clocks (n = 4, 5, 6, or 7).

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=6, and

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+4)

5-6

31.25 MHz

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=1, and

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+4)

7-10

125 MHz

Only for internal clocks (n = 4, 5, 6, or 7).

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=6, and

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+6)

SYNC_ETH_SD10G_CFG[DEV-7].SD10G_RCVRD_CLK_DIV=1

7-10

31.25 MHz

SYNC_ETH_CFG[n].RCVRD_CLK_ENA=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_DIV=1,

SYNC_ETH_CFG[n].SEL_RCVRD_CLK_SRC=(DEV+6), and

SYNC_ETH_SD10G_CFG[DEV-7].SD10G_RCVRD_CLK_DIV=1

Table 208 •

Recovered Clock Settings for 1 Gbps or Lower

Port

Output Frequency

VSC7440 Datasheet(PDF) 296 Page - Microsemi Corporation

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