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VSC7440 Datasheet(PDF) 302 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 302 Page - Microsemi Corporation

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Functional Descriptions
VMDS-10492 VSC7440 Datasheet Revision 4.2
285
3.29.3
Detecting Calculation Issues
A sticky bit per port informs if frames are received with the reserved bytes field non-zero. This can be
used to detect if incoming frames contain unexpected information in the reserved bytes field.
If the correction field is outside the valid range –247 to 247–1, another sticky bit is set in the port module
indicating the overflow. The port module replaces in this case the final CF with the overflow indication
value 247–1. This detection is however disabled when using ADDS48 mode because the correction field
in this mode rolls over regularly.
3.29.4
Two-Step Functions
The two-step PTP mode uses software as a middle stage for informing next hubs about residence times.
A FIFO of time stamping events is available for software where ingress and egress time stamps as well
as port numbers can be read out. The FIFO can contain 1,024 time stamp entries.
Figure 85 •
Time Stamp Bus and FIFO
The bus passes through all port modules and terminates in a timestamp FIFO in the rewriter. If the
analyzer has decided to do a two-step operation, the rewriter pushes two entries into the FIFO. The first
entry contains the egress time stamp and the egress port number; the second entry contains the ingress
time stamp and the ingress port number. In addition, a flag indicates whether the entry contains ingress
or egress information.
When correlating frames copied to the CPU with entries in the FIFO, the ingress time stamp found in the
IFH is the same as ingress time stamp found in the FIFO.
Note that the IDLY and EDLY values are not added to the CF field in the two-step case, as the frames are
transferred untouched. Software must manually add these delays for the follow-up frames.
3.29.5
Time of Day Time Stamping
When sending out SYNC frames with full TOD, the rewriter does the TOD time stamping at the time
where the frame passes through the rewriter and the port module is instructed to do a one-step update in
ADDS44
CF += (NSX44@rew)
CF += (CF_org(46)/=NSX48(44))?244:0
CF(46) = CF(47)
CF –= NSX44 CF(46) = NSX48(44)
ADDS48
CF += NSX48
CF –= NSX48
MONITOR
CF –= (NSF – IFH.TSTAMP)
DISABLED
NOP
Table 215 •
Rewriter Operations for One-Step Operation (continued)
Mode
Receiving From
Transmitting To
REW
DEV_0
DEV_1
DEV_n
Tx=1
Egress
PortNo
Egress
Timestamp
TS FIFO
Tx=0
Ingress
PortNo
Ingress
Timestamp
To S/W



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