VSC7440 datasheet(306/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

289

3.29.8.3 Port Module Registers

The following table lists the port module registers associated with time stamping. The

PTP_PHY_PREDICT_CFG register must be set for ports with internal PHYs.

3.29.9

Configuring I/O Delays

After a valid link is established and detected by the involved PCS logic, the I/O delays from the internal

time stamping points to the serial line must be configured. The delays are both mode-specific and

interface-specific, depending on the core clock frequency.

Ingress barrel shifter states that in 1G mode, the Rx delays must be added 0.8 ns times the value of

PCS1G_LINK_STATUS.DELAY_VAR to adjust for barrel shifting state after link establishment. In 2.5G

mode, the multiplier is 0.32 ns. In 100FX mode, the Rx delays must be subtracted 0.8 ns times the value

of PCS_FX100_STATUS.EDGE_POS_PTP to adjust for detected data phase.

The following tables provides the Rx and Tx delay times on the ports.

3.30

VRAP Engine

The Versatile Register Access Protocol (VRAP) engine allows external equipment to access registers in

the device through any of the Ethernet ports on the device. The VRAP engine interprets incoming VRAP

requests, and executes read, write, and read-modify-write commands contained in the frames. The

results of the register accesses are reported back to the transmitter through automatically generated

VRAP response frames.

Table 220 •

Port Module Registers

Description

PTP_CFG

Set I/O delays for port, enable PTP, and set port’s time domain.

PTP_EVENTS

Sticky bit for correction field overflow.

PTP_PHY_PREDICT_CFG

Configures the timing information delivered from the internal PHYs

on port 0 and port 1.

PTP_PHASE_PREDICT_CFG

Enables increased accuracy through clock phase evaluation.

Table 221 •

I/O Delays at 156.25 MHz

Port Number

100FX Mode

Rx/Tx

1G Mode

Rx/Tx

2.5G Mode

Rx/Tx

10G Mode

Rx/Tx

0 – 4

69.3/79.5

43.2/44.7

5, 6

78.2/80.8

51.7/43.9

22.0/14.1

7, 8

123.7/113.1

95.5/76.8

40.5/29.4

9, 10

123.7/113.1

95.5/76.8

39.9/29.2

111.8/162.1

Table 222 •

I/O Delays at 52 MHz

Port Number

100FX Mode

Rx/Tx

1G Mode

Rx/Tx

2.5G Mode

Rx/Tx

10G Mode

Rx/Tx

0 – 4

67.3/82.9

44.0/44.2

Does not apply

5, 6

75.4/83.3

52.2/44.2

Does not apply

7, 8

116.6/116.0

98.1/75.3

Does not apply

9, 10

116.6/116.0

98.1/75.3

Does not apply

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