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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

287

configurable high and low periods set in nanoseconds using the TimeOfDay watches or it can generate a

pulse at a configured time with a configurable duration and polarity.

In addition, the load operation can load a delta to the current time. This is done by executing a LOAD

action but using the DELTA command.

Each operation generates an interrupt when executed. For the clock action, the interrupt is generated

when the output switches to the active level. The interrupts from each controller can be masked and

monitored by the interrupt controller in the ICPU_CFG register target.

The five controllers are completely equal in their capabilities. For concatenated distributed TC

applications, two of the controllers are set up in STORE/sync mode, where incoming edges on the pin

make the Time of day be stored in the controller registers.

3.29.7

Multiple PTP Time Domains

For communicating with link partners running in another TOD domain, the device includes three PTP

time domains. Each port belongs to one domain only, and by default, all ports belong to time domain 0.

Other time domains are accessed by configuring the time domain in the port modules, the analyzer, the

rewriter, and the Loadstore controllers.

3.29.8

The following table lists the blocks and register configurations associated with IEEE 1588 functionality.

Table 216 •

LoadStore Controller

Pin Control Field

Function

Action

Load: Load TOD_SEC and TOD_NSEC through the absTime bus

Delta: Add configured nsec to the current time of day (absT).

Store: Store the current TOD_SEC,TOD_NSEC,TOD_NSF.

Clock: Generate a clock or a pulse on the pin.

Sync

Execute the load/store on incoming edge, if action is LOAD or STORE.

Generate a pulse instead of clock if action is CLOCK.

Inverse polarity

Falling edges are detected/generated.

TOD_sec

The 48-bit seconds of a time of day set to be loaded or stored.

TOD_nsec

The 30-bit nanoseconds of a time of day set to be loaded or stored.

TOD_NSF

The 32-bit free running timer to be stored (no load of that one)

Waveform high

Number of nanoseconds in the high period for generated clocks.

Duration of pulse for generated pulse.

Waveform_low

Number of nanoseconds in the low period for generated clocks.

Delay from TOD_ns = 0 for generated pulse.

Table 217 •

IEEE 1588 Configuration Registers Overview

Block

Configurations

Analyzer

PTP actions in VCAP IS2.

Rewriter

Path and asymmetry delays

Enabling use of preamble

Setting PTP port mode/options

Accessing time stamp FIFO

Port modules

Enable rewriting. Read barrel shifter states for accuracy.

I/O delays.

Per port SMAC for address replacing.

CPU device

Controlling TOD generation.

VSC7440 Datasheet(PDF) 304 Page - Microsemi Corporation

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