VSC7440 datasheet(343/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

326

The FDMA implements two extraction channels per CPU port and a total of eight injection channels.

Extraction channels are hard-coded per CPU port, and injection channels can be individually assigned to

any CPU port.

•

FDMA channel 0 corresponds to port 53 (group 0) extraction direction.

•

FDMA channel 1 corresponds to port 54 (group 1) extraction direction.

•

FDMA channel 2 through 9 corresponds to port 53 (group 0) injection direction when

FDMA_CH_CFG[channel].CH_INJ_GRP is set to 0.

•

FDMA channel 2 through 9 corresponds to port 54 (group 1) injection direction when

FDMA_CH_CFG[channel].CH_INJ_GRP is set to 1.

The FDMA implements a strict priority scheme. Injection and extraction channels can be assigned

individual priorities, which are used when the FDMA has to decide between servicing two or more

channels. Channel priority is configured in FDMA_CH_CFG[ch].CH_PRIO. When channels have same

priority, the higher channel number takes priority over the lower channel number.

When more than one injection channel is enabled for injection on the same CPU port, then priority

determines which channel that is allowed to inject data. Ownership is re-arbitrated on frame boundaries.

The internal frame header is added in front of extracted frames and provides useful switching information

about the extracted frames.

Injection frames requires an internal frame header for controlling injection parameters. The internal frame

header is added in front of frame data. The device recalculates and overwrites the Ethernet FCS for

frames that are injected via the CPU when requested by setting in the internal frame header.

For more information about the extraction and injection IFH, see Frame Headers, page 13.

The FDMA supports a manual mode where the FDMA decision logic is disabled and the FDMA takes and

provides data in the order that was requested by an external master (internal or external CPU). The

manual mode is a special case of normal FDMA operation where only few of the FDMA features apply.

For more information about manual operation, see Manual Mode.

The following configuration must be performed before enabling FDMA extraction: Set

XTR_GRP_CFG[group].MODE = 2.

The following configurations must be performed before enabling FDMA injection: Set

INJ_GRP_CFG[group].MODE = 2. Set INJ_CTRL[group].GAP_SIZE = 0, set

PORT_CFG[port].INJ_FORMAT_CFG = 1, set PORT_CFG[port].NO_PREAMBLE_ENA = 1, and set

PORT_CFG[port].VSTAX2_AWR_ENA = 0.

4.7.1

DMA Control Block Structures

The FDMA processes linked lists of DMA Control Block Structures (DCBs). The DCBs have the same

basic structure for both injection or for extraction. A DCB must be placed on a 32-bit word-aligned

address in memory. Each DCB must have an associated data block that is placed on a 32-bit word

aligned address in memory, the length of the data block must be a complete number of 32-bit words.

An Ethernet frame can be contained inside one data block (if the data block is big enough) or the frame

can be spread across multiple data blocks. A data block never contains more than one Ethernet frame.

Data blocks that contain start-of-frame have set a special bit in the DCB’s status word, likewise for data

blocks that contains end of frame. The FDMA stores or retrieves Ethernet frame data in network order.

This means that the data at byte address (n) of a frame was received just before the data at byte address

(n +1).

Frame data inside the DCB’s associated data blocks can be placed at any byte offset and have any byte

length as long as byte offset and length does not exceed the size of the data block. Byte offset and length

is configured using special fields inside the DCB status word. Software can specify offset both when

setting up extraction and injection DCBs. Software only specifies length for injection DCBs; the FDMA

automatically calculates and updates length for extraction.

Example If a DCB’s status word has block offset 5 and block length 2, then the DCB’s data block

contains two bytes of frame data placed at second and third bytes inside the second 32-bit word of the

DCB’s associated data block.

VSC7440 Datasheet(PDF) 343 Page - Microsemi Corporation

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