VSC7440 datasheet(340/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

323

Configure the low address of the destination window in PCIe memory space as follows:

•

Set ATU_TGT_ADDR_HIGH.ATU_TGT_ADDR_HIGH to bits [63:32] of the destination window. Set

to 0 when a 32-bit address must be generated.

•

Set ATU_TGT_ADDR_LOW.ATU_TGT_ADDR_LOW to bits [31:16] of the destination window. This

field must not be set higher than 0xC000.

Enable address translation by writing ATU_CFG2.ATU_REGION_ENA = 1. SBA access in the PCIe

DMA region is then mapped to PCIe memory space as defined by ATU_TGT_ADDR_LOW and

ATU_TGT_ADDR_HIGH.

The header fields and the PCIe address fields can be reconfigured on-the-fly as needed; however, set

ATU_REGION.ATU_IDX to 0 to ensure that the SBA region is selected.

4.6.5.2

Configuring Outbound FDMA Translation Region

Configure PCIESLV_FDMA.FDMA_OFFSET = 1, and select address translation region 1 by writing

ATU_REGION.ATU_IDX = 1.

Set PCIE::ATU_BASE_ADDR_LOW.ATU_BASE_ADDR_LOW = 0x4000 and

PCIE::ATU_LIMIT_ADDR.ATU_LIMIT_ADDR = 0x7FFF.

The FDMA PCIe header must be MRd/MWr type, reorderable, cache-coherent, and without ECRC.

Remaining header fields are automatically handled.

Configure low address of destination window in PCIe memory space as follows:

•

Set ATU_TGT_ADDR_HIGH.ATU_TGT_ADDR_HIGH to bits [63:32] of the destination window. Set

to 0 when a 32-bit address must be generated.

•

Set ATU_TGT_ADDR_LOW.ATU_TGT_ADDR_LOW to bits [31:16] of the destination window. This

field must not be set higher than 0xC000.

Enable address translation by writing ATU_CFG2.ATU_REGION_ENA = 1. The FDMA can be

configured to make access in the 0xC0000000 - 0xFFFFFFFF address region. These accesses will then

be mapped to PCIe memory space as defined by ATU_TGT_ADDR_LOW and ATU_TGT_ADDR_HIGH.

The FDMA must be disabled if the address window needs to be updated.

4.6.6

Power Management

The device’s PCIe endpoint supports D0, D1, and D3 device power-management states and associated

link power-management states. The switch core does not automatically react to changes in the PCIe

endpoint’s power management states. It is, however, possible to enable a VCore-III interrupt on device

Byte Enables

PCIESLV_SBA.SBA_BE

Message Code

ATU_CFG2.ATU_MSG_CODE

Table 241 •

FDMA PCIe Access Header Fields

Header Field

Suggested Value

Attributes

ATU_CFG1.ATU_ATTR

Set to 2

TLP Digest Field Present

ATU_CFG1.ATU_TD

Set to 0

Traffic Class

ATU_CFG1.ATU_TC

Use an appropriate traffic class

Type

ATU_CFG1.ATU_TYPE

Set to 0

Table 240 •

PCIe Access Header Fields (continued)

Header Field

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