VSC7440 datasheet(338/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

321

4.6.3

Base Address Registers Inbound Requests

The device implements three memory regions. Read and write operations using the PCIe are translated

directly to read and write access on the SBA. When manually bringing up the PCIe endpoint, BAR1 can

be disabled. For more information, see Manually Starting MAC/PCS and SerDes.

This region support all access types.

To access the BAR1 region, a Flash must be attached to the SI interface of the device. For information

about how to set up I/O timing and to program the Flash through BAR0; the Chip Registers Region, see

SI Boot Controller, page 333.

To access the BAR2 region, DDR3/DDR3L modules must be present and initialized. For information

about initializing the DDR3/DDR3L controller and modules through BAR0; the Chip Registers, see

DDR3/DDR3L Memory Controller. During manual bring up of PCIe, the size of the BAR2 region can be

changed to match the size of the attached DDR3/DDR3L modules. For more information, see Manually

Starting MAC/PCS and SerDes.

4.6.4

Outbound Interrupts

The device supports both Message Signaled Interrupt (MSI) and Legacy PCI Interrupt Delivery. The root

complex configures the desired mode using the MSI enable bit in the PCIe MSI Capability Register Set.

For information about the VCore-III interrupt controller, see Interrupt Controller, page 364.

The following table lists the device registers associated PCIe outbound interrupts.

In legacy mode, one interrupt is supported; select either EXT_DST0 or EXT_DST1 using

PCIE_INTR_COMMON_CFG.LEGASY_MODE_INTR_SEL. The PCIe endpoint uses Assert_INTA and

Deassert_INTA messages when configured for legacy mode.

In MSI mode, both EXT_DST interrupts can be used. EXT_DST0 is configured though

PCIE_INTR_CFG[0] and EXT_DST1 through PCIE_INTR_CFG[1]. Enable message generation on rising

and/or falling edges in PCIE_INTR_CFG[n].INTR_RISING_ENA and

PCIE_INTR_CFG[n].INTR_FALLING_ENA. Different vectors can be generated for rising and falling

edges, configure these through PCIE_INTR_CFG[n].RISING_VECTOR_VAL and

PCIE_INTR_CFG[n].FALLING_VECTOR_VAL. Finally, each EXT_DST interrupt must be given an

appropriate traffic class via PCIE_INTR_CFG[n].TRAFFIC_CLASS.

Table 237 •

Base Address Registers

Description

BAR0, 32-bit, 32 megabytes

Chip registers region. This region maps to the Chip registers

region in the SBA address space. See Chip Register Region.

This region only supports 32-bit word-aligned reads and

writes. Single and burst accesses are supported.

BAR1, 32-bit, 16 megabytes

SI Flash region. This region maps to the SI Flash region in the

SBA address space. See SI Flash Region.

This region only supports 32-bit word-aligned reads. Single

and burst access is supported.

BAR2, 32-bit, 128 megabytes

DDR3/DDR3L region. This region maps to the low 128

megabytes of the DDR3/DDR3L region in the SBA address

space. See DDR3/DDR3L Region.

Table 238 •

PCIe Outbound Interrupt Registers

Description

ICPU_CFG::PCIE_INTR_COMMON_CFG Interrupt mode and enable

ICPU_CFG::PCIE_INTR_CFG

MSI parameters

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