VSC7440 datasheet(335/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

318

The mailbox is a 32-bit register that can be set and cleared atomically using any CPU interface (including

the VCore-III CPU). The MAILBOX register allows reading (and writing) of the current mailbox value.

Atomic clear of individual bits in the mailbox register is done by writing a mask to MAILBOX_CLR. Atomic

setting of individual bits in the mailbox register is done by writing a mask to MAILBOX_SET.

The device implements two independent semaphores. The semaphores are part of the Switch Core

ownership can be taken by interfaces attached to the CSR. That is, the VCore-III, VRAP, SI, and MIIM

can be granted ownership. The VCore-III CPU and PCIe interface share the same semaphore, because

they both access the CSR through the switch core access block.

Any CPU attached to an interface can attempt to take a semaphore n by reading SEMA0.SEMA0 or

SEMA1.SEMA1. If the result is 1, the corresponding semaphore was successfully taken and is now

owned by that interface. If the result is 0, the semaphore was not free. After a successfully taking a

semaphore, all additional reads from the corresponding register will return 0. To release a semaphore

write 1 to SEMA0.SEMA0 or SEMA1.SEMA1.

Note: Any interface can release semaphores; it does not have to the one that has taken the semaphore. This

allows implementation of handshaking protocols.

The current status for a semaphore is available in SEMA0_OWNER.SEMA0_OWNER and

SEMA1_OWNER.SEMA1_OWNER. See register description for encoding of owners.

Software interrupt is generated when semaphores are free or taken. Interrupt polarity is configured

through SEMA_CFG.SEMA_INTR_POL. Semaphore 0 is hooked up to SW0 interrupt and semaphore 1

is hooked up to SW1 interrupt. For configuration of software-interrupt, see Interrupt Controller.

In addition to interrupting on semaphore state, software interrupt can be manually triggered by writing

directly to the ICPU_CFG::INTR_FORCE register.

Software interrupts (SW0 and SW1) can be individually mapped to either the VCore-III CPU or to

external interrupt outputs (to an external CPU).

4.6

PCIe Endpoint Controller

The device implements a single-lane PCIe 1.x endpoint that can be hooked up to any PCIe capable

system. Using the PCIe interface, an external CPU can access (and control) the device. Ethernet frames

can be injected and extracted using registers or the device can be configured to DMA Ethernet frames

autonomously to/from PCIe memory. The device’s DDR3/DDR3L memory is available through the PCIe

interface, allowing the external CPU full read and write access to DDR3/DDR3L modules attached to the

device. The DDR3/DDR3L controller and memory modules can be initialized either via PCIe or by the

VCore-III CPU.

Both the VCore-III CPU and Frame DMA can generate PCIe read/write requests to any 32-bit or 64-bit

memory region in PCIe memory space. However, it is up to software running on an external CPU to set

up or communicate the appropriate PCIe memory mapping information to the device.

The defaults for the endpoints capabilities region and the extended capabilities region are listed in the

registers list’s description of the PCIE registers. The most important parameters are:

•

Vendor (and subsystem vendor) ID: 0x101B, Microsemi Corporation

•

Device ID: 0xB004, device family ID

•

Revision ID: 0x00, device family revision ID

•

Class Code: 0x028000, Ethernet Network controller

•

Single function, non-Bridge, INTA and Message Signaled Interrupt (MSI) capable device

DEVCPU_ORG::SEMA1

Taking of semaphore 1.

DEVCPU_ORG::SEMA0_OWNER

Current owner of semaphore 0.

DEVCPU_ORG::SEMA1_OWNER

Current owner of semaphore 1.

Table 235 •

Mailbox and Semaphore Registers (continued)

Description

VSC7440 Datasheet(PDF) 335 Page - Microsemi Corporation

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