VSC7440 datasheet(333/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

316

The address of the register to read/write is set in registers ADDR_REG0 and ADDR_REG1. The data to

write to the register pointed to by the address in ADDR_REG0 and addr_reg1 is first written to

DATA_REG0 and then to DATA_REG1. When the write transaction to DATA_REG1 is completed, the

MIIM slave initiates the switch core register write.

With the register address of a specific register (REG_ADDR), the MIIM address (MIIM_ADDR) is

calculated as:

MIIM_ADDR = (REG_ADDR & 0x00FFFFFF)>>2

The following illustration shows a single MIIM write transaction on the MIIM interface.

Figure 107 •

MIIM Slave Write Sequence

A read transaction is done in a similar way. First, read the DATA_REG0 and then read the DATA_REG1.

As with a write operation. The switch core register read is not initiated before the DATA_REG1 register is

read. In other words, the returned read value is from the previous read transaction.

The following illustration shows a single MIIM read transaction on the MIIM interface.

Figure 108 •

MIIM Slave Read Sequence

4.5.4

Access to the VCore Shared Bus

This section provides information about how to access the VCore shared bus (SBA) from an external

CPU attached by means of the VRAP, SI, or MIIM. The following table lists the registers associated with

the VCore shared bus access.

An external CPU perform 32-bit reads and writes to the SBA through the VCore Access (VA) registers. In

the VCore-III system, a dedicated master on the shared bus handles VA access. For information about

arbitration between masters on the shared bus, see VCore Shared Bus Arbitration.

The SBA address is configured in VA_ADDR. Writing to VA_DATA starts an SBA write with the 32-bit

value that was written to VA_DATA. Reading from VA_DATA returns the current value of the register and

Table 234 •

VCore Shared Bus Access Registers

Description

DEVCPU_GCB::VA_CTRL

Status for ongoing access

DEVCPU_GCB::VA_ADDR

Configuration of shared bus address

DEVCPU_GCB::VA_DATA

Configuration of shared bus address

DEVCPU_GCB::VA_DATA_INCR

Data register, access increments VA_ADDR

DEVCPU_GCB::VA_DATA_INERT

Data register, access does not start new access

MDC

MDIO

PREAMBLE

32 bit

2 bit

PHYAD

5 bit

REGAD

5 bit

2 bit

DATA

16 bit

0101

MDC

MDIO

PREAMBLE

32 bit

2 bit

PHYAD

5 bit

REGAD

5 bit

2 bit

DATA

16 bit

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