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VSC7440 Datasheet(PDF) 330 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 330 Page - Microsemi Corporation

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VCore-III System and CPU Interfaces
VMDS-10492 VSC7440 Datasheet Revision 4.2
313
The following table lists the serial interface pins when the SI slave is configured as owner of SI interface
in GENERAL_CTRL.IF_SI_OWNER.
SI_DI is sampled on rising edge of SI_CLK. SI_DO is driven on falling edge of SI_CLK. There are no
requirements on the logical values of the SI_CLK and SI_DI inputs when SI_nCS is deasserted; they can
be either 0 or 1. SI_DO is only driven during read access when read data is shifted out of the device.
The external CPU initiates access by asserting chip select and then transmitting one bit read/write
indication, one don’t care bit, 22 address bits, and 32 bits of write data (or don’t care bits when reading).
With the register address of a specific register (REG_ADDR), the SI address (SI_ADDR) is calculated as:
SI_ADDR = (REG_ADDR & 0x00FFFFFF)>>2
Data word endianess is configured through IF_CTRL[0]. The order of the data bits is configured using
IF_CTRL[1].
The following illustration shows various configurations for write access. The order of the data bits during
writing, as depicted, is also used when the device is transmitting data during read operations.
Figure 103 •
Write Sequence for SI
When using the serial interface to read registers, the device needs to prepare read data after receiving
the last address bit. The access time of the register that is read must be satisfied before shifting out the
first bit of read data. For information about access time, see Register Access and Multimaster Systems.
The external CPU must apply one of the following solutions to satisfy read access time.
•
Use SI_CLK with a period of minimum twice the access time for the register target. For example, for
normal switch core targets (single master):
1/(2 × 1 µs) = 500 kHz (maximum)
Table 231 •
SI Slave Mode Pins
Pin Name
I/O
Description
SI_nCS0
I
Active-low chip select
SI_CLK
I
Clock input
SI_DI
I
Data input (MOSI)
SI_DO
O
Data output (MISO)
SI_nCS0
SI_CLK
SI_DI
SI_DO
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 987 654321 0
Serial Address (SI_ADDR)
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 98765 4 3 210
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
3
0
3
1
Serial Data
SI_DI
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 987 654321 0
Serial Address (SI_ADDR)
1
8
1
9
2
0
2
1
2
2
2
3 89
1
0
1
1
1
2
1
3
1
4
1
5 012 3 4 567
2
6
2
7
2
8
2
9
3
0
3
1
1
6
1
7
2
5
2
4
Serial Data
Big endian mode (IF_CTRL[0]=1), Most significant bit first (IF_CTRL[1]=0)
Big endian mode (IF_CTRL[0]=1), Least significant bit first (IF_CTRL[1]=1)
SI_DI
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
987 654321 0
Serial Address (SI_ADDR)
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
98
7 6543 2 1 0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
3
0
3
1
Serial Data
Little endian mode (IF_CTRL[0]=0), Most significant bit first (IF_CTRL[1]=0)
SI_DI
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 987 654321 0
Serial Address (SI_ADDR)
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
234 5 6 789
1
0
Serial Data
Little endian mode (IF_CTRL[0]=0), Least significant bit first (IF_CTRL[1]=1)



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