VSC7440 datasheet(332/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

315

The MIIM slave interface allows an external CPU to perform read and write access to the device register

targets. Register access is done indirectly, because the address and data fields of the MIIM protocol is

less than those used by the register targets. Transfers on the MIIM interface are using the Management

Frame Format protocol specified in IEEE 802.3, Clause 22.

The MIIM slave pins on the device are overlaid functions on the GPIO interface. MIIM slave mode is

enabled by configuring the appropriate VCore_CFG strapping pins. For more information, see VCore-III

Configurations, page 306. When MIIM slave mode is enabled, the appropriate GPIO pins are

automatically overtaken. For more information about overlaid functions on the GPIOs for these signals,

see GPIO Overlaid Functions, page 352.

The following table lists the pins of the MIIM slave interface.

MIIM_SLV_MDIO is sampled or changed on the rising edge of MIIM_SLV_MDC by the MIIM slave

interface.

The MIIM slave can be configured to answer on one of two different PHY addresses using

ICPU_CFG::GENERAL_CTRL.IF_MIIM_SLV_ADDR_SEL or the VCore_CFG strapping pins.

The MIIM slave has seven 16-bit MIIM registers defined as listed in the following table.

A 32-bit switch core register read or write transaction over the MIIM interface is done indirectly due to the

limited data width of the MIIM frame. First, the address of the register inside the device must be set in the

two 16-bit address registers of the MIIM slave using two MIIM write transactions. The two 16-bit data

registers can then be read or written to access the data value of the register inside the device. Thus, it

requires up to four MIIM transactions to perform a single read or write operation on a register target.

Table 232 •

MIIM Slave Pins

Pin Name

I/O

Description

MIIM_SLV_MDC/GPIO

MIIM slave clock input

MIIM_SLV_MDIO/GPIO

I/O

MIIM slave data input/output

Table 233 •

MIIM Registers

Description

ADDR_REG0

Bits 15:0 of the address to read or write. The address field must be

formatted as word address.

ADDR_REG1

Bits 31:16 of the address to read or write.

DATA_REG0

Bits 15:0 of the data to read or write. Returns 0x8888 if a register read

error occurred.

DATA_REG1

Bits 31:16 of the data to read or write. The read or write operation is

initiated after this register is read or written. Returns 0x8888 if read while

busy or a register read error occurred.

DATA_REG1_INCR Bits 31:16 of data to read or write. The read or write operation is initiated

after this register is read or written. When the operation is complete, the

address register is incremented by one. Returns 0x8888 if read while

busy or a register read error occurred.

DATA_REG1_INERT Bits 31:16 of data to read or write. Reading or writing to this register does

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