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VSC7440 Datasheet(PDF) 331 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 331 Page - Microsemi Corporation

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VCore-III System and CPU Interfaces
VMDS-10492 VSC7440 Datasheet Revision 4.2
314
•
Pause the SI_CLK between shifting of serial address bit 0 and the first data bit with enough time to
satisfy the access time for the register target.
•
Configure the device to send out padding bytes before transmitting the read data to satisfy the
access time for the register target. For example, 1 dummy byte allows enough read time for the SI
clock to run up to 6 MHz in a single master system. See the following calculation.
The device is configured for inserting padding bytes by writing to IF_CFGSTAT.IF_CFG. These bytes are
transmitted before the read data. The maximum frequency of the SI clock is calculated as:
(IF_CFGSTAT.IF_CFG × 8 – 1.5)/access-time
For example, for normal switch core targets (single master), 1-byte padding give(1 × 8 – 1.5)
/1 µs = 6 MHz (maximum). The SI_DO output is kept tri-stated until the actual read data is transmitted.
The following illustrations show options for serial read access. The illustrations show only one mapping
of read data, little endian with most significant bit first. Any of the mappings can be configured and
applied to read data in the same way as for write data.
Figure 104 •
Read Sequence for SI_CLK Slow
Figure 105 •
Read Sequence for SI_CLK Pause
Figure 106 •
Read Sequence for One-Byte Padding
When dummy bytes are enabled (IF_CFGSTAT.IF_CFG), the SI slave logic enables an error check that sends out
0x88888888 and sets IF_CFGSTAT.IF_STAT if the SI master does not provide enough time for register read.
When using SI, the external CPU must configure the IF_CTRL register after power-up, reset, or chip-level soft reset.
The IF_CTRL register is constructed so that it can be written no matter the state of the interface. For more information
about constructing write data for this register, see the instructions in IF_CTRL.IF_CTRL.
4.5.3
MIIM Interface in Slave Mode
This section provides the functional aspects of the MIIM slave interface.
SI_nCS0
SI_CLK
SI_DI
SI_DO
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 98765 43 210
Serial Address (SI_ADDR)
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 98 76 5 4 3 2 10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
3
0
3
1
Serial Data
Big endian mode (IF_CTRL[0]=1), Most significant bit first (IF_CTRL[1]=0), no padding (IF_CFGSTAT.IF_CFG=0)
SI_nCS0
SI_CLK
SI_DI
SI_DO
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 98765 4 3 21 0
Serial Address (SI_ADDR)
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 987654 3 2 10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
3
0
3
1
Serial Data
Big endian mode (IF_CTRL[0]=1), Most significant bit first (IF_CTRL[1]=0), no padding (IF_CFGSTAT.IF_CFG=0)
pause
SI_nCS0
SI_CLK
SI_DI
SI_DO
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 98765 4 3 21 0
Serial Address (SI_ADDR)
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 987654 3 2 10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
3
0
3
1
Serial Data
Big endian mode (IF_CTRL[0]=1), Most significant bit first (IF_CTRL[1]=0), one-byte padding (IF_CFGSTAT.IF_CFG=1)
padding (1 byte)



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