VSC7440 datasheet(328/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

311

4.3.4

DDR3/DDR3L Region

Read and write access from or to the DDR3/DDR3L region maps to access on the DDR3 interface of the

device using the DDR3 controller. For more information about the DDR3/DDR3L controller and initializing

DDR3/DDR3L memory, see DDR3/DDR3L Memory Controller.

4.3.5

PCIe Region

Read and write access from or to the PCIe region maps to outbound read and write access on the PCIe

interface of the device by means of the PCIe endpoint controller. For more information about the PCIe

endpoint controller and how to reach addresses in 32-bit and 64-bit PCIe environments, see PCIe

Endpoint Controller.

4.4

VCore-III CPU

The VCore-III CPU system is based on a powerful MIPS24KEc-compatible microprocessor with 16-entry

MMU, 32 kilobytes (kB) instruction, and 32 kB data caches.

This section describes how the VCore-III CPU is integrated into the VCore-III system. For more

information about internal VCore-III CPU functions, such as bringing up caches, MMU, and so on, see

the software board support package (BSP) at www.microsemi.com.

When the automatic boot in the little-endian or big-endian mode is enabled using the VCore-III strapping

pins, the VCore-III CPU automatically starts to execute code from the SI Flash at byte address 0.

The following is a typical automatic boot sequence.

Speed up the boot interface. For more information, see SI boot controller.

Initialize the DDR3/DDR3L controller. For more information, see DDR3/DDR3L Memory Controller

Copy code-image from Flash to DDR3/DDR3L memory.

Change memory map from boot mode to normal mode, see Shared Bus.

When automatic boot is disabled, an external CPU is still able to start the VCore-III CPU through

registers. For more information, see VCore Configurations.

The boot vector of the VCore-III CPU is mapped to the start of the KESEG1, which translates to physical

address 0x00000000 on the VCore-III shared bus.

The VCore-III CPU interrupts are mapped to interrupt inputs 0 and 1, respectively.

4.4.1

Little Endian and Big Endian Support

The VCore-III system is constructed as a little endian system, and registers descriptions reflect little

endian encoding. When big endian mode is enabled, instructions and data are byte-lane swapped just

before they enter and when they leave the VCore-III CPU. This is the standard way of translating

between a CPU in big endian mode and a little endian system.

In big endian mode, care must be taken when accessing parts of the memory system that is also used by

users other than the VCore-III CPU. For example, device registers are written and read by the VCore-III

CPU, but they are also used by the device (which sees them in little endian mode). The VCore-III BSP

contains examples of code that correctly handles register access for both little and big endian mode.

Endianess of the CPU is selected by VCore-III strapping pins or by register configuration when manually

booting the CPU. For more information, see VCore-III configurations.

4.4.2

Software Debug and Development

The VCore CPU has a standard MIPS EJTAG debug interface that can be used for breakpoints, loading

of code, and examining memory. When the JTAG_ICE_nEN strapping pin is pulled low, the JTAG

interface is attached to the EJTAG controller.

4.5

External CPU Support

An external CPU attaches to the device through the PCIe, SI, MIIM, or VRAP. Through these interfaces,

an external CPU can access (and control) the device. For more information about interfaces and

connections to device registers, see VCore-III system block diagram.

VSC7440 Datasheet(PDF) 328 Page - Microsemi Corporation

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