VSC7440 datasheet(324/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

307

The device can be soft reset by writing SOFT_RST.SOFT_CHIP_RST. The VCore-III system and CPU

can be protected from a device soft reset by writing RESET.CORE_RST_PROTECT = 1 before initiating

a soft reset. In this case, a chip-level soft reset is applied to all other blocks, except the VCore-III system

and the CPU. When protecting the VCore-III system and CPU from a soft reset, the frame DMA must be

disabled prior to a chip-level soft reset. The SERDES and PLL blocks can be protected from reset by

writing to SOFT_RST.SOFT_SWC_RST instead of SOFT_CHIP_RST.

The VCore-III general purpose registers (ICPU_CFG::GPR) and GPIO alternate modes

(DEVCPU_GCB::GPIO_ALT) are not affected by a soft reset. These registers are only reset when an

external reset is asserted.

4.2.1

Watchdog Timer

The VCore system has a built-in watchdog timer (WDT) with a two-second timeout cycle. The watchdog

timer is enabled, disabled, or reset through the WDT register. The watchdog timer is disabled by default.

After the watchdog timer is enabled, it must be regularly reset by software. Otherwise, it times out and

cause a VCore soft reset equivalent to setting RESET.CORE_RST_FORCE. Improper use of the

WDT.WDT_LOCK causes an immediate timeout-reset as if the watchdog timer had timed out. The

WDT.WDT_STATUS field shows if the last VCore-III CPU reset was caused by WDT timeout or regular

reset (possibly soft reset). The WDT.WDT_STATUS field is updated only during VCore-III CPU reset.

To enable or to reset the watchdog timer, write the locking sequence, as described in WDT.WDT_LOCK,

at the same time as setting the WDT.WDT_ENABLE field.

Because watchdog timeout is equivalent to setting RESET.CORE_RST_FORCE, the

RESET.CORE_RST_CPU_ONLY field also applies to watchdog initiated soft reset.

4.3

Shared Bus

The shared bus is a 32-bit address and 32-bit data bus with dedicated master and slave interfaces that

interconnect all the blocks in the VCore-III system. The VCore-III CPU, PCIe inbound, and VCore SBA

access block are masters on the shared bus; only they can start access on the bus.

The shared bus uses byte addresses, and transfers of 8, 16, or 32 bits can be made. To increase

performance, bursting of multiple 32-bit words on the shared bus can be performed.

All slaves are mapped into the VCore-III system’s 32-bit address space and can be accessed directly by

masters on the shared bus. Two possible mappings of VCore-III shared bus slaves are boot mode and

normal mode.

•

Boot mode is active after power-up and reset of the VCore-III system. In this mode, the SI Flash boot

master is mirrored into the lowest address region.

•

In normal mode, the DDR3/DDR3L controller is mirrored into the lowest address region.

Changing between boot mode and normal mode is done by first writing and then reading

ICPU_CFG::GENERAL_CTRL.BOOT_MODE_ENA. A change takes effect during the read.

The device supports up to 1 gigabyte (GB) of DDR3/DDR3L memory. By default, only 512 megabytes

(MB) is accessible in the memory map. To accommodate more than 512 MB of memory, write

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