VSC7440 datasheet(323/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

306

4.1

VCore-III Configurations

The behavior of the VCore-III system after a reset is determined by four VCore strapping pins that are

overlaid on GPIO pins. The value of these GPIOs is sampled shortly after releasing reset to the device.

For more information about the strapping pins, see Pin Strapping, page 303.

The strapping value determines the reset value for the ICPU_CFG::GENERAL_CTRL register. After

startup, the behavior of the VCore-III system can be modified by changing some of the fields in this

•

After starting the device with the VCore-III CPU disabled, an external CPU can manually boot the

VCore-III CPU from SI Flash by writing ICPU_CFG::GENERAL_CTRL.IF_SI_OWNER = 1,

ICPU_CFG::GENERAL_CTRL.BOOT_MODE_ENA = 1, and

ICPU_CFG::GENERAL_CTRL.CPU_DIS = 0. Endianess is configured by

ICPU_CFG::GENERAL_CTRL.CPU_BE_ENA. Setting GENERAL_CTRL.IF_SI_OWNER disables

the SI slave, so the external CPU must use another interface than SI.

•

After starting the device with the VCore-III CPU disabled and loading software into DDR3/DDR3L

memory, an external CPU can boot the VCore-III CPU from DDR3/DDR3L memory by writing

ICPU_CFG::GENERAL_CTRL.BOOT_MODE_ENA = 0 and

ICPU_CFG::GENERAL_CTRL.CPU_DIS = 0. Endianess is configured using

ICPU_CFG::GENERAL_CTRL.CPU_BE_ENA.

•

After automatically booting from SI Flash, the VCore-III CPU can release the SI interface and enable

the SI slave by writing ICPU_CFG::GENERAL_CTRL.IF_SI_OWNER = 0. This enables SI access

from an external CPU to the device. A special PCB design is required to make the serial interface

work for both Flash and external CPU access.

•

MIIM slave can be manually enabled by writing

ICPU_CFG::GENERAL_CTRL.IF_MIIM_SLV_ENA = 1. The MIIM slave automatically takes control

of the appropriate GPIO pins.

The EJTAG interface of the VCore-III CPU and the Boundary Scan JTAG controller are both multiplexed

onto the JTAG interface of the device. When the JTAG_ICE_nEN pin is low, the MIPS’s EJTAG controller

is selected. When the JTAG_ICE_nEN pin is high, the Boundary Scan JTAG controller is selected.

4.2

Clocking and Reset

The following table lists the registers associated with reset and the watchdog timer.

The VCore-III CPU runs 500 MHz, the DDR3/DDR3L controller runs 312.50 MHz, and the rest of the

VCore-III system runs at 250 MHz.

The VCore-III can be soft reset by setting RESET.CORE_RST_FORCE. By default, this resets both the

VCore-III CPU and the VCore-III system. The VCore-III system can be excluded from a soft reset by

setting RESET.CORE_RST_CPU_ONLY; soft reset using CORE_RST_FORCE only then resets the

VCore-III CPU. The frame DMA must be disabled prior to a soft reset of the VCore-III system. When

CORE_RST_CPU_ONLY is set, the frame DMA, PCIe endpoint, and DDR3/DDR3L controller are not

affected by a soft reset and continue to operate throughout soft reset of the VCore-III CPU.

The VCore-III system comprises all the blocks attached to the VCore Shared Bus (SBA), including the

PCIe, DDR3/DDR3L, and frame DMA/injection/extraction blocks. Blocks attached to the switch core

domain. For more information about the VCore-III system blocks, see Figure 99, page 305.

Table 229 •

Clocking and Reset Configuration Registers

Description

ICPU_CFG::RESET

VCore-III reset protection scheme and initiating soft reset of

the VCore-III system and/or CPU.

DEVCPU_GCB::SOFT_RST

Initiating chip-level soft reset.

ICPU_CFG::WDT

Watchdog timer configuration and status.

VSC7440 Datasheet(PDF) 323 Page - Microsemi Corporation

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