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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

309

4.3.1

VCore-III Shared Bus Arbitration

The following table lists the registers associated with the shared bus arbitration.

The VCore-III shared bus arbitrates between masters that want to access the bus. The default is to use a

strict prioritized arbitration scheme where the VCore-III CPU has highest priority. The strict priorities can

be changed using registers PL_CPU, PL_PCIE, and PL_CSR.

•

*_CPU registers apply to VCore-III CPU access

•

*_PCIE registers apply to inbound PCIe access

•

*_CSR registers apply to VCore-III SBA access block access

It is possible to enable weighted token arbitration scheme (WT_EN). When using this scheme, specific

masters can be guaranteed a certain amount of bandwidth on the shared bus. Guaranteed bandwidth

that is not used is given to other masters requesting the shared bus.

When weighted token arbitration is enabled, the masters on the shared bus are grated a configurable

number of tokens (WT_CPU, WT_PCIE, and WT_CSR) at the start of each refresh period. The length of

each refresh period is configurable (WT_TCL). For each clock cycle that the master uses the shared bus,

the token counter for that master is decremented. When all tokens are spent, the master is forced to a

low priority. Masters with tokens always take priority over masters with no tokens. The strict prioritized

scheme is used to arbitrate between masters with tokens and between masters without tokens.

Example Guarantee That PCIe Can Get 25% Bandwidth. Configure WT_TCL to a refresh period of

2048 clock cycles; the optimal length of the refresh period depends on the scenario, experiment to find

the right setting. Guarantee PCIe access in 25% of the refresh period by setting WT_PCIE to 512 (2048

× 25%). Set WT_CPU and WT_CSR to 0. This gives the VCore-III CPU and CSR unlimited tokens.

Configure PCIe to highest priority by setting PL_PCIe to 15. Finally, enable the weighted token scheme

by setting WT_EN to 1. For each refresh period of 2048 clock cycles, PCIe is guaranteed access to the

shared bus for 512 clock cycles, because it is the highest priority master. When all the tokens are spend,

it is put into the low-priority category.

4.3.2

Chip Register Region

Registers in the VCore-III domain and inside the switch core are memory mapped into the chip registers

region of the shared bus memory map. All registers are 32-bit wide and must only be accessed using 32-

bit reads and writes. Bursts are supported.

Writes to this region are buffered (there is a one-word write buffer). Multiple back-to-back write access

pauses the shared bus until the write buffer is freed up (until the previous writes are done). Reads from

this region pause the shared bus until read data is available.

Table 230 •

Shared Bus Configuration Registers

Description

SBA::PL_CPU

Master priorities

SBA::PL_PCIE

Master priorities

SBA::PL_CSR

Master priorities

SBA::WT_EN

Enable of weighted token scheme

SBA::WT_TCL

Weighted token refresh period

SBA::WT_CPU

Token weights for weighted token scheme

SBA::WT_PCIE

Token weights for weighted token scheme

SBA::WT_CSR

Token weights for weighted token scheme

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